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AD9528BCPZ датащи(PDF) 14 Page - Analog Devices

номер детали AD9528BCPZ
подробное описание детали  JESD204B Clock Generator with 14 LVDS/HSTL Outputs
PDF  67 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9528BCPZ датащи(HTML) 14 Page - Analog Devices

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AD9528
Data Sheet
Rev. D | Page 14 of 67
SERIAL CONTROL PORT—I2C MODE
Table 18.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SDA, SCL VOLTAGE
When inputting data
Input Logic 1
0.7 × VDD
V
Input Logic 0
0.3 × VDD
V
Input Current
−10
+10
µA
Input voltage between 0.1 × VDD and
0.9 × VDD
Hysteresis of Schmitt Trigger Inputs
0.015 ×
VDD
V
SDA
When outputting data
Output Logic 0 Voltage at 3 mA Sink
Current
0.2
V
Output Fall Time from VIHMIN to
VILMAX
20 + 0.1 CB1
250
ns
Bus capacitance from 10 pF to 400 pF
TIMING
All I2C timing values are referred to VIHMIN
(0.3 × VDD) and VILMAX levels (0.7 × VDD)
Clock Rate (SCL, fI2C)
400
kHz
Bus Free Time Between a Stop and
Start Condition
tIDLE
1.3
µs
Setup Time for a Repeated Start
Condition
tSET; STR
0.6
µs
Hold Time (Repeated) Start
Condition
tHLD;STR
0.6
µs
After this period, the first clock pulse is
generated
Setup Time for a Stop Condition
tSET; STP
0.6
µs
Low Period of the SCL Clock
tLOW
1.3
µs
High Period of the SCL Clock
tHIGH
0.6
µs
SCL, SDA Rise Time
tRISE
20 + 0.1 CB1
300
ns
SCL, SDA Fall Time
tFALL
20 + 0.1 CB1
300
ns
Data Setup Time
tSET; DAT
100
ns
Data Hold Time
tHLD; DAT
0
ns
Capacitive Load for Each Bus Line
CB1
400
pF
1 CB is the capacitance of one bus line in picofarads (pF).



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