AD9528BCPZ datasheet(4/67 Pages) AD

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AD9528

Data Sheet

Rev. D | Page 4 of 67

SPECIFICATIONS

The AD9528 is configured for dual loop mode. The REFA differential input is enabled at 122.88 MHz, fVCXO = 122.88 MHz and single-

ended, fVCO = 3686.4 MHz, VCO divider = 3. Doubler and analog delay are off, SYSREF generation is on, unless otherwise noted. Typical

is given for VDDx = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDDx

and TA (−40°C to +85°C) variation, as listed in Table 1.

CONDITIONS

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY VOLTAGE

VDDx1

3.135

3.3

3.465

3.3 V ± 5%

TEMPERATURE

Ambient Temperature

Range, TA

−40

+25

+85

°C

Junction Temperature, TJ

+115

°C

Refer to the Power Dissipation and Thermal Considerations section to

calculate the junction temperature

1 VDDx includes the VDD pins (Pin 1, Pin 10, Pin 16, Pin 20, and Pin 72) and the VDD13 pin through the VDD0 pin, unless otherwise noted. See the Pin Configuration and Function

Descriptions for details.

SUPPLY CURRENT

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY CURRENT

Excludes clock distribution section; clock distribution outputs running as follows:

7 HSTL device clocks at 122.88 MHz, 7 LVDS SYSREF clocks (3.5 mA) at 960 kHz

Dual Loop Mode

PLL1 and PLL2 enabled

VDD (Pin 1, Pin 72)

VDD (Pin 10)

VDD (Pin 16)

VDD ( Pin 20)

Single Loop Mode

PLL1 off and REFA and REFB inputs off

VDD (Pin 1, Pin 72)

122.88 MHz reference source applied to the VCXO inputs (input to PLL2)

VDD (Pin 10)

VDD (Pin 16)

VDD (Pin 20)

Buffer Mode

PLL1 and PLL2 off, REFA and REFB inputs disabled; 122.88 MHz reference source

applied to VCXO differential inputs to drive 7 of 14 outputs, internal SYSREF

generator off, 960 kHz input source applied to SYSREF differential inputs to drive

the other 7 outputs, dividers in clock distribution path bypassed in clock

distribution channel

VDD (Pin 1, Pin 72)

VDD (Pin 10)

VDD (Pin 16)

VDD (Pin 20)

Chip Power-Down

Mode

VDD (Pin 1, Pin 10,

Pin 16, Pin 20,

and Pin 72)

Chip power-down bit enabled (Register 0x0500, Bit 0 = 1)

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