AD9528BCPZ datasheet(5/67 Pages) AD

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Data Sheet

AD9528

Rev. D | Page 5 of 67

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY CURRENT FOR

EACH CLOCK

DISTRIBUTION

CHANNEL

Each clock output channel has a dedicated VDD pin. The current draw for each

VDD pin includes the divider, fine delay, and output driver, fine delay is off; see the

Pin Configuration and Function Descriptions section for pin assignment

LVDS Mode, 3.5 mA

Output = 122.88 MHz, channel divider = 10

Output = 409.6 MHz, channel divider = 3

Output = 737.28 MHz, channel divider = 1, VCO divider = 5, LVDS boost mode of

4.5 mA recommended

LVDS Boost Mode,

4.5 mA

Output = 122.88 MHz, channel divider =10

Output = 409.6 MHz, channel divider = 3

Output = 737.28 MHz, channel divider = 1, VCO divider = 5

HSTL Mode, 9 mA

Output = 122.88 MHz, channel divider =10

Output = 409.6 MHz, channel divider = 3

Output = 983.04 MHz, channel divider = 1, VCO divider = 5, VCO = 3932.16 MHz

Output = 1228.8 MHz, channel divider = 1, only output channels OUT1 and OUT2

support output frequencies greater than ~1 GHz

Chip Power-Down

Mode

2.5

For each channel VDD pin, chip power-down bit enabled (Register 0x0500, Bit 0 = 1)

POWER DISSIPATION

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TOTAL POWER

DISSIPATION

Does not include power dissipated in termination resistors

Typical Dual Loop

Mode Configuration

1675

1780

Differential REFA input at 122.88 MHz; fVCXO = 122.88 MHz, fVCO = 3686.4 MHz, VCO

divider at 3 clock distribution outputs running as follows: 7 HSTL at 122.88 MHz,

7 LVDS (3.5 mA) at 960 kHz

Typical Single Loop

Mode

Configuration

1635

1810

PLL1 off, differential VCXO input at 122.88 MHz, clock distribution outputs running

as follows: 7 HSTL at 122.88 MHz, 7 LVDS (3.5 mA) at 960 kHz

Typical Buffer Mode

1030

1200

PLL1 and PLL2 off, differential VCXO input at 122.88 MHz. SYSREF generator off,

differential SYSREF input at 960 kHz; clock distribution outputs running as follows:

7 HSTL at 122.88 MHz, 7 LVDS (3.5 mA) at 960 kHz

Chip Power-Down

Mode

Chip power-down bit enabled (Register 0x0500, Bit 0 = 1)

RESET Enabled

1015

1200

RESET pin low

INCREMENTAL POWER

DISSIPATION

Does not include power dissipated in termination resistors

Low Power Base

Configuration

590

Dual loop mode, SYSREF generation and fine delay off; total power with 1 LVDS

output running at 122.88 MHz, single-ended REFA at 122.88 MHz; REFB off,

VCXO = 122.88 MHz, VCO = 3686.4 MHz

PLL1 OFF

Define settings to power off PLL1

Output Distribution

Incremental power increase for each additional enable output

LVDS Mode, 3.5 mA

Single 3.5 mA LVDS output at 122.88 MHz, channel divider = 10

Single 3.5 mA LVDS output at 409.6 MHz, channel divider = 3

Single 3.5 mA LVDS output at 737.28 MHz, VCO divider = 5, channel divider = 1

LVDS Mode, 4.5 mA

Single 4.5 mA LVDS output at 122.88 MHz, channel divider = 10

Single 4.5 mA LVDS output at 409.6 MHz, channel divider = 3

Single 4.5 mA LVDS output at 737.28 MHz, VCO divider = 5

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