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AD9528BCPZ датащи(PDF) 13 Page - Analog Devices

номер детали AD9528BCPZ
подробное описание детали  JESD204B Clock Generator with 14 LVDS/HSTL Outputs
PDF  67 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9528BCPZ датащи(HTML) 13 Page - Analog Devices

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Data Sheet
AD9528
Rev. D | Page 13 of 67
SERIAL CONTROL PORT—SERIAL PORT INTERFACE (SPI) MODE
Table 17.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
CS (INPUT)
CS has an internal 35 kΩ pull-up resistor
Voltage
Input Logic 1
1.37
V
Input Logic 0
1.33
V
Current
Input Logic 1
−52
µA
Input Logic 0
−82
µA
Input Capacitance
2
pF
SCLK (INPUT) IN SPI MODE
SCLK has an internal 40 kΩ pull-down
resistor in SPI mode but not in I2C mode
Voltage
Input Logic 1
1.76
V
Input Logic 0
1.22
V
Current
Input Logic 1
0.0037
µA
Input Logic 0
0.0012
µA
Input Capacitance
2
pF
SDIO
Input is in bidirectional mode
Voltage
Input Logic 1
1.76
V
Input Logic 0
1.22
V
Current
Input Logic 1
0.0037
µA
Input Logic 0
0.0012
µA
Input Capacitance
3.5
pF
SDIO, SDO (OUTPUTS)
Voltage
Output Logic 1
3.11
V
Output Logic 0
0.0018
V
TIMING
Clock Rate (SCLK, 1/tSCLK)
50
MHz
Pulse Width High
tHIGH
4
ns
Pulse Width Low
tLOW
2
ns
SDIO to SCLK Setup
tDS
2.2
ns
SCLK to SDIO Hold
tDH
−0.9
ns
SCLK to Valid SDIO and SDO
tDV
6
ns
CS to SCLK Setup
tS
1.25
ns
CS to SCLK Hold
tC
0
ns
CS Minimum Pulse Width High
tPWH
0.9
ns



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