AD9528BCPZ datasheet(59/67 Pages) AD

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Data Sheet

AD9528

Rev. D | Page 59 of 67

CLOCK DISTRIBUTION (REGISTER 0x300 TO REGISTER 0x0329)

Table 57. Channel 0 to Channel 13 Control (This Same Map Applies to All 14 Channels)

Address

Bits

Bit Name

Description

0x0300,

0x0303,

0x0306,

0x0309,

0x030C,

0x030F,

0x0312,

0x0315,

0x0318,

0x031B,

0x031E,

0x0321,

0x0324,

0x0327

[7:5]

Channel control, Bits[2:0]

Controls which signal source is selected by the output driver.

Bit 7

Bit 6

Bit 5

Output Signal Source

PLL2/divider output.

PLL1/VCXO output.

SYSREF (retimed by PLL2 output).

SYSREF (retimed by PLL1 output).

PLL2/divider output.

Inverted PLL1/VCXO output.

SYSREF (retimed by PLL2 output).

SYSREF (retimed by inverted PLL1 output).

Fine analog delay enable

1 = enables fine delay for the corresponding channel. 600 ps insertion delay.

0 (default) = disables fine analog delay for the corresponding channel.

[3:0]

Fine analog delay, Bits[3:0]

15 fine delay steps.

Step size = 31 ps.

0x0301,

0x0304,

0x0307,

0x030A,

0x030D,

0x0310,

0x0313,

0x0316,

0x0319,

0x031C,

0x031F,

0x0322,

0x0325,

0x0328

[7:6]

Output format, Bits[1:0]

Determines the output logic to be applied.

Bit 7

Bit 6

Output Logic Type

LVDS.

LVDS (boost mode).

HSTL.

[5:0]

Coarse digital delay, Bits[5:0]

Divider initial phase after a sync is asserted relative to the divider input clock (from the

VCO divider output). LSB = ½ of a period of the divider input clock.

Phase = 0: no phase offset.

Phase = 1: ½ period offset

…

Phase = 63: 31.5 period offset.

0x0302,

0x0305,

0x0308,

0x030B,

0x030E,

0x031A,

0x0314,

0x0317,

0x031A,

0x031D,

0x0320,

0x0323,

0x0326,

0x0329

[7:0]

Divide ratio, Bits[7:0] (LSB)

Division = Channel divider Bits[7:0] + 1. For example, [7:0] = 0 is divided by 1, [7:0] = 1

is divided by 2…[7:0] = 255 is divided by 256. 8-bit channel divider.

Table 58. Distribution Sync

Address

Bits

Bit Name

Description

0x032A

[7:1]

Reserved

Reserved.

SYNC outputs

Issues SYNC on transition of bit 0 from 1 to 0.

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