AD9528BCPZ datasheet(7/67 Pages) AD

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Data Sheet

AD9528

Rev. D | Page 7 of 67

VCXO_VT OUTPUT CHARACTERISTICS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT VOLTAGE

High

VDD − 0.15

RLOAD > 20 kΩ

Low

150

PLL2 CHARACTERISTICS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VCO (ON CHIP)

Frequency Range

3450

4025

MHz

Gain

MHz/V

PLL2 FIGURE OF MERIT (FOM)

−226

dBc/Hz

MAXIMUM PFD FREQUENCY

275

MHz

CLOCK DISTRIBUTION OUTPUT CHARACTERISTICS

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

HSTL MODE

Output Frequency

1000

MHz

All outputs

1250

MHz

OUT0 to OUT3, OUT12, OUT13 outputs only

Rise Time/Fall Time (20% to 80%)

160

100 Ω termination across output pair

Duty Cycle

f < 500 MHz

f = 500 MHz to 800 MHz

f = 800 MHz to 1.25 GHz

If using PLL2

Differential Output Voltage Swing

900

1000

1100

VOH − VOL for each leg of a differential

pair for default amplitude setting with

the driver not toggling; the peak-to-

peak amplitude measured using a

differential probe across the differential

pair with the driver toggling is roughly

2× these values (see Figure 5 for

variation over frequency)

Common-Mode Output Voltage

0.88

0.9

0.94

LVDS MODE, 3.5 mA

3.5 mA

Output Frequency

1000

MHz

All outputs

1250

GHz

OUT0 to OUT3, OUT12, OUT13 outputs only

Rise Time/Fall Time (20% to 80%)

216

100 Ω termination across output pair

Duty Cycle

f < 500 MHz

f = 500 MHz to 800 MHz

f = 800 MHz to 1.25 GHz

Balanced, Differential Output

Swing (VOD)

345

390

Voltage swing between output pins;

output driver static (see Figure 6 for

variation over frequency)

Unbalanced, ∆VOD

Absolute difference between voltage

swing of normal pin and inverted pin;

output driver static

Common-Mode Output Voltage

1.15

1.35

Common-Mode Difference

1.2

Voltage difference between output pins;

output driver static

Short-Circuit Output Current

Output driver static

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