EM78P568

8-bit OTP Micro-controller

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* This specification are subject to be changed without notice.

7

01/31/2004

V4.7

P80 ~ P87

I/O

PORT8 can be INPUT or OUTPUT port each bit.

Internal pull high.

PORT85 ~ P87 are shared with ADC input

PORT8(0~3) have wake-up functions(set by RE PAGE0)

P90 ~ P97

I/O

PORT9 can be INPUT or OUTPUT port each bit.

PORT9 are shared with LCD Segment signal.

PB0 ~ PB7

I/O

PORTB can be INPUT or OUTPUT port each bit.

PORTB are shared with LCD Segment signal.

PC0 ~ PC7

I/O

PORTC can be INPUT or OUTPUT port each bit.

PORTC(7:5) are shared with LCD Segment signal.

INT0

(PORT70)

Interrupt sources. Once PORT70 has a falling edge or rising edge signal

(controlled by CONT register), it will generate a interruption.

INT1

(PORT71)

Interrupt sources which has the same interrupt flag. Any pin from PORT71

has a falling edge signal, it will generate a interruption.

INT2

(PORT72)

Interrupt sources which has the same interrupt flag. Any pin from PORT72

has a falling edge signal, it will generate a interruption.

INT3

(PORT73)

Interrupt sources which has the same interrupt flag. Any pin from PORT73

has a falling edge signal, it will generate a interruption.

/RESET

I

Low reset