EM78P568

8-bit OTP Micro-controller

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* This specification are subject to be changed without notice.

48

01/31/2004

V4.7

VII.11 8-bit R-2R DAC

DAST/P67

PORT67

DAO/P67

DATEN

MUX

2.5V

ref

VDD

REFSEL

REFEN

B2

B1

2R

2R

R

2R

2R

R

8-bit

DAC

input

data

buffer

(This circuit is from Comparator)

VRSEL

To ladder resistors

CMPEN

(This circuit is from CTCSS)

MUX

ASW3

VTX3

VRX3

To Sub-Audio LPF

MUX

DAC input

MUX

DA7~DA0

DAT/DAD

(part of DAC Tone Gen.)

DAC tone gen

Name

Register bit location

DA7 ~ DA0

RA PAGE1 bit 7 ~ 0

DAT/DAD

IOCA PAGE1 bit 7

Name

Register bit location

DAST/P67

IOCA PAGE1 bit 3

DATEN

IOCA PAGE1 bit 5

ps. Please refer to “Voltage reference control logic” to set DAC reference.

Fig.22 DAC block

In DAC tone generator mode, user can get CTCSS tone output. In other case, DAC is useful in general tone

generation such as key tone, alert tone, music and so on. In DAC general mode, only VREF and DAST/P67 bits are

relative to DAC reference voltage. DAC reference voltage is come from VDD or 2.5V ref. Setting VREF bit (IOCE

PAGE1 bit 6) = 0/1 to select VDD/2.5V as reference. Setting DAST/P67 bit = 1 to power on DAC and also enable

output buffer B1. After that, DAC output signal will be sent to DAO/P67 pin.