EM78P568

8-bit OTP Micro-controller

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* This specification are subject to be changed without notice.

40

01/31/2004

V4.7

The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling

interrupts to avoid recursive interrupts.

VII.8 Instruction Set

Instruction set has the following features:

(1) Every bit of any register can be set, cleared, or tested directly.

(2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O

register.

The symbol "R" represents a register designator which specifies which one of the 64 registers (including

operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4

determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit,

located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value.

INSTRUCTION BINARY

HEX

MNEMONIC

OPERATION

STATUS

AFFECTED

Instruction

cycle

0

0000

0000

0000

0000

NOP

No Operation

None

1

0

0000

0000

0001

0001

DAA

Decimal Adjust A

C

1

0

0000

0000

0010

0002

CONTW

A

→ CONT

None

1

0

0000

0000

0011

0003

SLEP

0

→ WDT, Stop oscillator

T,P

1

0

0000

0000

0100

0004

WDTC

0

→ WDT

T,P

1

0

0000

0000

rrrr

000r

IOW R

A

→ IOCR

None

1

0

0000

0001

0000

0010

ENI

Enable Interrupt

None

1

0

0000

0001

0001

0011

DISI

Disable Interrupt

None

1

0

0000

0001

0010

0012

RET

[Top of Stack]

→ PC

None

2

0

0000

0001

0011

0013

RETI

[Top of Stack]

→ PC

Enable Interrupt

None

2

0

0000

0001

0100

0014

CONTR

CONT

→ A

None

1

0

0000

0001

rrrr

001r

IOR R

IOCR

→ A

None

1

0

0000

0010

0000

0020

TBL

R2+A

→ R2 bits 9,10 do not

clear

Z,C,DC

2

0

0000

0011

0000

0030

MUL

(MR) (+/-) (s/us X)*(s/us Y)

→ MR

None

1

0

0000

01rr

rrrr

00rr

MOV R,A

A

→ R

None

1

0

0000

1000

0000

0080

CLRA

0

→ A

Z

1

0

0000

11rr

rrrr

00rr

CLR R

0

→ R

Z

1

0

0001

00rr

rrrr

01rr

SUB A,R

R-A

→ A

Z,C,DC

1

0

0001

01rr

rrrr

01rr

SUB R,A

R-A

→ R

Z,C,DC

1

0

0001

10rr

rrrr

01rr

DECA R

R-1

→ A

Z

1

0

0001

11rr

rrrr

01rr

DEC R

R-1

→ R

Z

1

0

0010

00rr

rrrr

02rr

OR A,R

A

∨ VR → A

Z

1

0

0010

01rr

rrrr

02rr

OR R,A

A

∨ VR → R

Z

1

0

0010

10rr

rrrr

02rr

AND A,R

A & R

→ A

Z

1

0

0010

11rr

rrrr

02rr

AND R,A

A & R

→ R

Z

1