AD9675KBCZ datasheet(15/61 Pages) AD

15 / 61 page

AD9675

Data Sheet

Rev. A | Page 14 of 60

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

B5, B6, B8, C5, C6, C7, C8, D5, D6, D7, D8,

E1, E5, E6, E7, E8, E12, F2, F4, F6, F7, F9,

F11, G1, G3, G5, G6, G7, G8, G10, G12,

H3, H4, H5, H6, J4, K1, K2, K4, M1, M12

GND

Ground. These pins are tied to a quiet analog ground.

F1, F3, F5, F8, F10, F12, G2, G9

AVDD1

1.8 V Analog Supply.

G4, G11

DVDD

1.4 V Digital Supply.

E2, E3, E4, E9, E10, E11, J6, K6

AVDD2

3.0 V Analog Supply.

CLNA

LNA External Capacitor.

L1, L12

DRVDD

1.8 V Digital Output Driver Supply.

LO-E

LNA Analog Inverted Output for Channel E.

LOSW-E

LNA Analog Switched Output for Channel E.

LI-E

LNA Analog Input for Channel E.

LG-E

LNA Ground for Channel E.

LO-F

LNA Analog Inverted Output for Channel F.

LOSW-F

LNA Analog Switched Output for Channel F.

LI-F

LNA Analog Input for Channel F.

LG-F

LNA Ground for Channel F.

LO-G

LNA Analog Inverted Output for Channel G.

LOSW-G

LNA Analog Switched Output for Channel G.

LI-G

LNA Analog Input for Channel G.

LG-G

LNA Ground for Channel G.

LO-H

LNA Analog Inverted Output for Channel H.

LOSW-H

LNA Analog Switched Output for Channel H.

LI-H

LNA Analog Input for Channel H.

LG-H

LNA Ground for Channel H.

CLK−

Clock Input Complement.

CLK+

Clock Input True.

TX_TRIG−

Transmit Trigger Complement.

TX_TRIG+

Transmit Trigger True.

H11

ADDR0

Chip Address Bit 0.

H10

ADDR1

Chip Address Bit 1.

ADDR2

Chip Address Bit 2.

ADDR3

Chip Address Bit 3.

ADDR4

Chip Address Bit 4.

L2, M2, L3, M3, L10, M10, L11, M11

NIC

Not Internally Connected. These pins are not connected internally. Allow the

NIC pins to float, or connect them to ground. Avoid routing high speed signals

through these pins because noise coupling may result.

SYNCINB+

Active Low JESD204B LVDS SYNC Input—True.

SYNCINB−

Active Low JESD204B LVDS SYNC Input—Complement.

SERDOUT4−

Serial Lane 4 CML Output Data—Complement.

SERDOUT4+

Serial Lane 4 CML Output Data—True.

SERDOUT3−

Serial Lane 3 CML Output Data—Complement.

SERDOUT3+

Serial Lane 3 CML Output Data—True.

SERDOUT2−

Serial Lane 2 CML Output Data—Complement.

SERDOUT2+

Serial Lane 2 CML Output Data—True.

SERDOUT1−

Serial Lane 1 CML Output Data—Complement.

SERDOUT1+

Serial Lane 1 CML Output Data—True.

SYSREF−

Active Low JESD204B LVDS System Reference (SYSREF) Input—Complement.

SYSREF+

Active Low JESD204B LVDS SYSREF Input—True.

K11

STBY

Standby Power-Down.

J11

PDWN

Full Power-Down.

K12

SCLK

Serial Clock.

J12

SDIO

Serial Data Input/Output.

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