AD9675KBCZ datasheet(31/61 Pages) AD

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AD9675

Data Sheet

Rev. A | Page 30 of 60

Figure 45. AD9675 Transmit Link Simplified Block Diagram

Figure 45 shows a simplified block diagram of the AD9675

JESD204B link. By default, the AD9675 is configured to use

eight channels and four lanes. Channel A and Channel B data is

output to SERDOUT1±, Channel C and Channel D data is

output to SERDOUT2±, Channel E and Channel F data is

output to SERDOUT3±, and Channel G and Channel H data is

output to SERDOUT4±. The AD9675 allows other configura-

tions such as combining the outputs of the eight channels onto a

single lane.

By default in the AD9675, the 14-bit converter word from each

converter is broken into two octets (eight bits of data). Bit 0

(MSB) through Bit 7 are in the first octet. The second octet

contains Bit 8 through Bit 13 (LSB) and two tail bits. The tail

bits can be configured as zeros or a pseudorandom number

sequence.

The two resulting octets can be scrambled. Scrambling is optional

but is available to avoid spectral peaks when transmitting similar

digital data patterns. The scrambler uses a self synchronizing

polynomial-based algorithm defined by the equation: 1 + x14 + x15.

The descrambler in the receiver must be a self synchronizing

version of the scrambler polynomial.

The two octets are then encoded with an 8-bit/10-bit encoder. The

8-bit/10-bit encoder works by taking eight bits of data (an octet)

and encoding them into a 10-bit symbol. Figure 46 shows how

the 14-bit data is taken from the ADC, the tail bits are added, the

two octets are scrambled, and how the octets are encoded into

two 10-bit symbols. Figure 46 illustrates the default data format.

At the data link layer, in addition to the 8-bit/10-bit encoding,

the character replacement allows the receiver to monitor frame

alignment. The character replacement process occurs on the

frame and multiframe boundaries, and implementation depends

on which boundary is occurring and if scrambling is enabled.

If scrambling is disabled, the following applies. If the last

scrambled octet of the last frame of the multiframe equals the

last octet of the previous frame, the transmitter replaces the last

octet with the control character /A/ = /K28.3/. On other frames

within the multiframe, if the last octet in the frame equals the

last octet of the previous frame, the transmitter replaces the last

octet with the control character /F/ = /K28.7/.

If scrambling is enabled, the following applies. If the last octet of

the last frame of the multiframe equals 0x7C, the transmitter

replaces the last octet with the control character /A/ = /K28.3/.

On other frames within the multiframe, if the last octet equals

0xFC, the transmitter replaces the last octet with the control

character /F/ = /K28.7/.

Refer to JEDEC Standard JESD204B (July 2011) for additional

information about the JESD204B interface. Section 5.1

describes the transport layer and data format details, and

Section 5.2 describes scrambling and descrambling.

JESD204B Synchronization Details

The AD9675 is a JESD204B Subclass 0 device and establishes

synchronization of the link through three control signals,

SYNCINB, TX_TRIG, optionally SYSREF, and typically a

common device clock. SYNCINB, TX_TRIG, and SYSREF are

assumed to be common to all converter devices for alignment

purposes at the system level.

The synchronization process is accomplished over three phases:

code group synchronization (CGS) phase, initial lane alignment

sequence (ILAS) phase, and data transmission phase. Note that

if scrambling is enabled, the bits are not actually scrambled

until the data transmission phase. The CGS and ILAS phases do

not use scrambling.

CGS Phase

In this phase, the JESD204B transmit block transmits /K28.5/

characters in response to a synchronization request from the

receiver (SYNCINB signal asserted). The receiver (external

logic device) must locate K28.5 characters in its input data

stream using clock and data recovery (CDR) techniques.

After a certain number of consecutive K28.5 characters are

detected on all link lanes, the receiver can optionally initiate a

SYS_REF edge so that the AD9675 transmit data establishes a

local multiframe clock (LMFC) internally. The AD9675 is a

subclass 0 device that does not mandate SYS_REF for multi-

device synchronization. The use of SYS_REF reduces the

latency variation between devices and reduce the absolute

latency of each device to some extent. However, SYS_REF does

not meet the full requirements of a JESD204B subclass 1 device,

and the primary synchronization tool on the AD9675 is to use

the global TX_TRIG signal that embed a START_CODE into

the data stream simultaneously for all devices.

After synchronizing all lanes, the receiver or logic device

deasserts the SYNCINB signal (SYNCINB± goes high), and the

transmitter block begins the ILAS phase, if enabled, on the next

internal LMFC boundary.

ILAS Phase

In the ILAS phase, the transmitter sends out a known pattern

and the receiver aligns all lanes of the link and verifies the

parameters of the link.

OUTPUT

SAMPLES

FROM CHANNEL

TRANSPORT

LAYER

DATA LINK

LAYER

PHYSICAL

LAYER

SCRAMBLER

SERIALIZER

FRAME

CONSTRUCTION

8-BIT/10-BIT

ENCODER

SAMPLE

CONSTRUCTION

LANE

ALIGNMENT

CHARACTER

GENERATION

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