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Data Sheet

AD9675

Rev. A | Page 31 of 60

The ILAS phase begins after SYNCINB± is deasserted (goes

high). The transmit block begins to transmit four multiframes.

Dummy samples are inserted between the required characters

so that full multiframes are transmitted.

The four multiframes have the following properties:



Multiframe 1 begins with an /R/ character (K28.0) and

ends with an /A/ character (K28.3).



Multiframe 2 begins with an /R/ character, followed by a /Q/

(K28.4) character and link configuration parameters over

14 configuration octets (see Table 15), and ends with an

/A/ character. Many of the parameter values are of the

notation of the value − 1.



Multiframe 3 is the same as Multiframe 1.



Multiframe 4 is the same as Multiframe 1.

Data Transmission Phase

By the end of the ILAS phase, data transmission starts.

Initiating a global TX_TRIG signal resets any sampling edges

within the ADC and replaces a sample with the START_CODE

(see Address 0x18B and Address 0x18C in Table 31). Aligning

the data on all lanes based on the START_CODE guarantees the

synchronization across multiple lanes and across multiple

devices.

In the data transmission phase, frame alignment is monitored

with control characters. Character replacement is used at the

end of frames. Character replacement in the transmitter occurs

in the following instances:



If scrambling is disabled and the last octet of the frame or

multiframe equals the octet value of the previous frame.



If scrambling is enabled and the last octet of the multiframe is

equal to 0x7C, or the last octet of a frame is equal to 0xFC.

Table 15. 14 Configuration Octets of the ILAS Phase

No.

Bit 7

(MSB)

Bit

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

N'[4:0]

S[4:0]

CF[4:0]

Reserved, don’t care

FCHK[7:0]

Link Setup Parameters

The following steps demonstrate how to configure the AD9675

JESD204B interface and the outputs.

Disable lanes before changing the configuration

Select the converter and lane configuration

Configure the tail bits and control bits

Set the lane identification values

Set the number of frame per multiframe, K

Enable scramble, SCR

Set the lane synchronization options

Check FCHK, checksum of JESD204B interface parameters

Set additional digital output configuration options

10. Reenable lane(s) after configuration

Disable Lanes

Before modifying the JESD204B link parameters, disable the

link and hold it in reset. This is accomplished by writing a

Logic 1 to Address 0x142, Bit 0.

Converter and Lane Configuration

The JESD204B M parameter (number of converters) is set to 8

(Address 0x153 = 0x07).

The lane configuration is set in Address 0x150, Bits[1:0] such

that 00 = one lane per link, 01 = two lanes per link, or 11 = four

lanes per link. The channel data (A to H) is placed on the

JESD204B lanes according Table 16.

Table 16. Channel to JESD204B Lane Mapping

SERDOUT1±

SERDOUT2±

SERDOUT3±

SERDOUT4±

A, B, C, D, E, F,

G, H

Power-down

A, B, C, D

Power-down

E, F, G, H

Power-down

A, B

C, D

E, F

G, H

Configure the Tail Bits and Control Bits

With N' = 16 and N = 14, two tail bits are available per sample

for transmitting additional information over the JESD204B link.

Tail bits are dummy bits sent over the link to complete the two

octets and do not convey any information about the input signal.

Tail bits can be fixed zeros (default) or pseudorandom numbers

(Address 0x142, Bit 6).

Set Lane Identification Values

JESD204B allows parameters to identify the device and lane.

These parameters are transmitted during the ILAS phase, and they

are accessible in the internal registers.

There are three identification values: device identification

(DID), bank identification (BID), and lane identification (LID).

DID and BID are device specific; therefore, they can be used for

link identification.

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