AD9675KBCZ datasheet(28/61 Pages) AD

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Data Sheet

AD9675

Rev. A | Page 27 of 60

AAF/VGA Test Mode

For debug and testing, there is a bypass switch to view the AAF

output on the GPO2 and GPO3 pins. Enable this mode via SPI

Address 0x109, Bit 4. The differential AAF output of only one

channel can be accessed at a time. The dc output voltage is 1.5 V

(or AVDD2/2) and the maximum ac output voltage is 2 V p-p.

ADC

The AD9675 uses a pipelined ADC architecture. The quantized

output from each stage is combined into a 14-bit result in the

digital correction logic. The pipelined architecture permits the

first stage to operate on a new input sample and the remaining

stages to operate on preceding samples. Sampling occurs on the

rising edge of the clock.

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The data is then serialized

and aligned to the frame and output clocks.

Clock Input Considerations

For optimum performance, clock the AD9675 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled into the CLK+ and CLK− pins via a

transformer or capacitors. These pins are biased internally and

require no additional bias.

Figure 39 shows the preferred method for clocking the AD9675.

A low jitter clock source, such as the Valpey Fisher oscillator,

VFAC3AHL-1 80.000, is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD9675 to approximately 0.8 V p-p differential. This

prevents the large voltage swings of the clock from feeding

through to other portions of the AD9675, and it preserves the

fast rise and fall times of the signal, which are critical to low

jitter performance.

Figure 39. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac couple a

differential positive emitter-coupled logic (PECL) signal to the

sample clock input pins, as shown in Figure 40. Analog Devices

offers clock drivers with excellent jitter performance, such as

the AD9516-0 or the AD9524.

Figure 40. Differential PECL Sample Clock

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 41.

Figure 41. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

drive CLK+ directly from a CMOS gate, and bypass the CLK−

pin to ground with a 0.1 μF capacitor (see Figure 42).

Figure 42. Single-Ended 1.8 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs can

be sensitive to the clock duty cycle. Commonly, a 5% tolerance

is required on the clock duty cycle to maintain dynamic

performance characteristics. The AD9675 contains a duty cycle

stabilizer (DCS) that retimes the nonsampling edge, providing

an internal clock signal with a nominal 50% duty cycle. This

allows a wide range of clock input duty cycles without affecting

the performance of the AD9675. When the DCS is on, noise

and distortion performance are nearly flat for a wide range of

duty cycles. However, some applications may require the DCS

function to be off. When the DCS function is off, the dynamic

range performance can be affected.

The duty cycle stabilizer uses a delay-locked loop (DLL) to create

the nonsampling edge. As a result, any changes to the sampling

frequency require approximately eight clock cycles to allow the

DLL to acquire and lock to the new rate.

0.1µF

SCHOTTKY

DIODES:

HSM2812

3.3V

50Ω

100Ω

CLK–

CLK+

ADC

MINI-CIRCUITS®

ADT1-1WT, 1:1Z

XFMR

VFAC3

OUT

100Ω

0.1µF

240Ω

AD9524/AD9516-0

CLK

*50Ω RESISTOR IS OPTIONAL.

PECL DRIVER

3.3V

OUT

VFAC3

CLK–

CLK+

ADC

50Ω*

100Ω

0.1µF

AD9524/AD9516-0

CLK

*50Ω RESISTOR IS OPTIONAL.

LVDS DRIVER

3.3V

OUT

VFAC3

CLK–

CLK+

ADC

50Ω*

0.1µF

OPTIONAL

100Ω

0.1µF

CMOS DRIVER

0.1µF

CLK

*50Ω RESISTOR IS OPTIONAL.

AD9524/AD9516-0

3.3V

OUT

VFAC3

CLK–

CLK+

ADC

50Ω*

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