AD9675KBCZ datasheet(38/61 Pages) AD

38 / 61 page

Data Sheet

AD9675

Rev. A | Page 37 of 60

Digital Output Test Patterns

Figure 55. Example of Data Flow Block Diagram

Table 21. Flexible Output Test Modes—Address 0x00D

Output Test

Mode Bit

Sequence

Pattern Name

Digital Output

Word 1

Digital Output

Word 2

Digital Output

Word 3

Digital Output

Word 4

Subject to

Resolution

Select

0000

Off (default)

Not applicable

0001

Midscale short

10 0000 0000 0000

Same

Yes

0010

+Full-scale short

11 1111 1111 1111

Same

Yes

0011

−Full-scale short

00 0000 0000 0000

Same

Yes

0100

Checkerboard

output

10 1010 1010 1010

01 0101 0101 0101

10 1010 1010 1010

01 0101 0101 0101

0101

PN sequence

long

Not applicable

Yes

0110

PN sequence

short

Not applicable

Yes

0111

One-/zero-word

toggle

11 1111 1111 1111

00 0000 0000 0000

11 1111 1111 1111

00 0000 0000 0000

1000

User input

Address 0x019 and

Address 0x01A

Address 0x01B and

Address 0x01C

Address 0x01D and

Address 0x01E

Address 0x01F and

Address 0x020

1001 to 1110

Reserved

Not applicable

1111

Ramp output

00 0000 0000 0000

00 0000 0000 0001

00 0000 0000 0000

00 0000 0000 0001

Yes

Table 22. Flexible Output Test Modes—Address 0x144

Output Test

Mode Bit

Sequence

Pattern Name

Digital Output

Word 1

Digital Output

Word 2

Digital Output

Word 3

Digital Output

Word 4

Subject to

Resolution

Select

0000

Off (default)

Not applicable

0001

Alternating

checkerboard

10 1010 1010 1010

01 0101 0101 0101

10 1010 1010 1010

01 0101 0101 0101

0010

One-/zero-word

toggle

11 1111 1111 1111

00 0000 0000 0000

11 1111 1111 1111

00 0000 0000 0000

0011

PN sequence long

Not applicable

Yes

0100

PN sequence

short

Not applicable

Yes

0101

Continuous/

repeat user test

pattern

Address 0x019 and

Address 0x01A

Address 0x01B and

Address 0x01C

Address 0x01D and

Address 0x01E

Address 0x01F and

Address 0x020

0110

Single user test

pattern

Address 0x019 and

Address 0x01A

Address 0x01B and

Address 0x01C

Address 0x01D and

Address 0x01E

Address 0x01F and

Address 0x020

0111

Ramp output

00 0000 0000 0000

00 0000 0000 0001

00 0000 0000 0000

00 0000 0000 0001

Yes

1000

Modified RPAT

sequence

See JESD204B

specification

See JESD204B

specification

See JESD204B

specification

See JESD204B

specification

Not applicable

1001 to 1111

Reserved

Not applicable

SAMPLE

CONSTRUCTION

SERIALIZER

TEST

PATTERNS

OUTPUT

PROCESSED

SAMPLE FROM

ADC

8-BIT/10-BIT

ENCODER

TEST

PATTERNS

FRAME/LANE

ALIGNMENT

CHARACTER

GENERATION

SCRAMBLER

FRAME

CONSTRUCTION

TEST

PATTERNS

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