AD9675KBCZ datasheet(35/61 Pages) AD

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AD9675

Data Sheet

Rev. A | Page 34 of 60

Frame and Lane Alignment Monitoring and Correction

Frame alignment monitoring and correction is part of the

JESD204B specification. The 14-bit word requires two octets to

transmit all the data. The two octets (MSB and LSB), where

F = 2, make up a frame. During normal operating conditions,

frame alignment is monitored via alignment characters that are

inserted under certain conditions at the end of a frame. Table 19

summarizes the conditions for character insertion along with

the expected characters under the various operation modes. If

lane synchronization is enabled, the replacement character

value depends on whether the octet is at the end of a frame or at

the end of a multiframe.

Based on the operating mode, the receiver can ensure that it is

still synchronized to the frame boundary by correctly receiving

the replacement characters.

Digital Outputs and Timing

The AD9675 has differential digital outputs that power up by

default. The driver current is derived on chip and sets the

output current at each output equal to a nominal 4 mA. Each

output presents a 100 Ω dynamic internal termination to reduce

unwanted reflections.

The AD9675 digital outputs can interface with custom ASICs and

FPGA receivers, providing superior switching performance in

noisy environments. Single point-to-point network topologies are

recommended with a single differential 100 Ω termination resistor

placed as close to the receiver logic as possible.

For receiver inputs that provide their own common-mode bias,

or whose input common-mode requirements are not within the

bounds of the AD9675 DRVDD supply, use an ac-coupled

connection as shown in Figure 47. Place a 0.1 μF series

capacitor on each output pin and use a 100 Ω differential

termination close to the receiver side. The 100 Ω differential

termination results in a nominal 600 mV p-p differential swing

at the receiver. In the case where the receiver inputs do not

provide their own common mode bias, single-ended 50 Ω

terminations can be used. When single-ended terminations are

used, the termination voltage (VRXCM) must be chosen to match

the input requirements of the receiver.

For receivers whose input common mode voltage requirements

match the output common-mode voltage (DRVDD/2) of the

AD9675, a dc-coupled connection can be used. The common

mode of the digital output automatically biases itself to half of

DRVDD (0.9 V for DRVDD = 1.8 V) (see Figure 48).

If there is no far end receiver termination or if there is poor

differential trace routing, timing errors may result. To avoid

such timing errors, it is recommended that the trace length be

less than six inches and that the differential output traces be

adjacent and at equal lengths.

Figure 49 to Figure 54 show examples of the digital output

(default) data eye and a time interval error (TIE) jitter histogram.

Figure 47. AC-Coupled Digital Output Termination Example

Figure 48. DC-Coupled Digital Output Termination Example

100Ω

50Ω

100Ω

DIFFERENTIAL

SINGLE-ENDED

TERMINATION

TRACE PAIR

SERDOUTx+

DRVDD

VRXCM

SERDOUTx–

VCM = Rx VCM

OUTPUT SWING = 600mV p-p

RECEIVER

0.1µF

100Ω

DIFFERENTIAL

TRACE PAIR

DRVDD

VCM = DRVDD/2

OUTPUT SWING = 600mV p-p

RECEIVER

SERDOUTx+

SERDOUTx–

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