AR0141CS

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43

Table 31.

Parameter

Unit

Max

Typ

Min

Symbol

cap Termination

50

mV

Termination

30

mV

V

Maximum Overshoot Vdiff pk−pk

V

Single−ended Output Impedance

35

50

70

Ω

Output Impedance Mismatch

20

%

Table 32.

SLVS ELECTRICAL TIMING SPECIFICATION

Parameter

Symbol

Min

Max

Unit

Data Rate (Note 1)

1/UI

280

600

Mbps

Bitrate Period (Note 1)

1.43

3.57

ns

Max Setup Time from Transmitter (Note 1, 2)

0.3

UI

Max Hold Time from Transmitter (Note 1, 2)

0.3

UI

Eye Width (Note 1, 2)

0.6

UI

Data Total Jitter (pk−pk) @1e−9 (Note 1, 2)

0.2

UI

Clock Period Jitter (RMS) (Note 2)

50

ps

Clock Cycle−to−Cycle Jitter (RMS) (Note 2)

100

ps

Rise Time (20% − 80%) (Note 3)

150ps

0.25

UI

Fall Time (20% − 80%) (Note 3)

150ps

0.25

UI

Clock Duty Cycle (Note 2)

45

55

%

Mean Clock to Data Skew (Note 1, 4)

−0.1

0.1

UI

PHY−to−PHY Skew (Note 1, 5)

2.1

UI

Mean Differential Skew (Note 6)

−100

100

ps

1. One UI is defined as the normalized mean time between one edge and the following edge of the clock.

2. Taken from the 0V crossing point with the DLL off.

3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates

so the rise and fall times do not exceed the maximum 0.3 UI.

4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.

5. The absolute skew between any Clock in one PHY and any Data lane in any other PHY between any edges.

6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two

complementary edges at mean VCM point. Note that differential skew also is related to the

Figure 46. Differential Output Voltage for Clock or Data Pairs

0V Diff)

VDIFFmax

VDIFFmin

Output Signal is ’Cp − Cn’ or ’Dp − Dn’