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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AR0141CS датащи(PDF) 38 Page - ON Semiconductor |
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AR0141CS датащи(HTML) 38 Page - ON Semiconductor |
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38 / 48 page  AR0141CS www.onsemi.com 38 I/O Timing By default, the AR0141CS launches pixel data, FV, and LV with the falling edge of PIXCLK. The expectation is that the user captures DOUT[11:0], FV, and LV using the rising edge of PIXCLK. See Figure 45 for I/O timing diagram. Figure 45. I/O Timing Diagram Data[11:0] FRAME_VALID/ LINE_VALID FRAME_VALID leads LINE_VALID by 6 PIXCLKs. FRAME_VALID trails LINE_VALID by 6 PIXCLKs. PIXCLK EXTCLK 90 % 10 % 90 % 10 % tPD tPD Pxl_0 Pxl_1 Pxl_2 Pxl_n tPFH tPLH tPFL tPLL tEXTCLK tR tF tRP tFP Table 19. I/O TIMING CHARACTERISTICS (2.8 V VDD_IO) (Conditions: fPIXCLK = 37.125 MHz (720P30fps; VDD_IO = 2.8 V) Symbol Definition Condition Min Typ Max Unit fEXTCLK1 Input clock frequency PLL enabled 6 – 50 MHz tEXTCLK1 Input clock period PLL enabled 20 – 166 ns tR Input clock rise time – 3 – ns tF Input clock fall time – 3 – ns tRR PIXCLK rise time PCLK slew rate setting = 2 2.0 3.5 6.4 ns tFP PIXCLK fall time PCLK slew rate setting = 2 1.9 3.3 6.2 ns Clock duty cycle 45 50 55 % tJITTER2 Input clock jitter at 27 MHz – – 600 ps fPIXCLK PIXCLK frequency default PLL configuration 6 37.125 74.25 MHz tPD PIXCLK to Data[11:0] PCLK slew rate setting = 2 parallel slew rate setting = 4 −2.0 – 5.9 ns tPFH PIXCLK to FV high PCLK slew rate setting = 2 parallel slew rate setting = 2 −0.9 – 4.4 ns tPLH PIXCLK to LV high PCLK slew rate setting = 2 parallel slew rate setting = 2 −0.8 – 4.6 ns tPFL PIXCLK to FV low PCLK slew rate setting = 2 parallel slew rate setting = 2 −1.5 – 3.1 ns tPLL PIXCLK to FV low PCLK slew rate setting = 2 parallel slew rate setting = 2 −1.5 – 3.3 ns CLOAD Output load capacitance – 30 – pF CIN Input pin capacitance – 2.5 – pF 1. Slew rate setting = 2 for PIXCLK Slew rate setting = 2 for parallel ports |
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