AR0141CS datasheet(6/48 Pages) ONSEMI

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AR0141CS

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Table 3. BALL DESCRIPTIONS, 9 X 9 MM, 63−BALL iBGA

Name

Description

Type

iBGA Pin

VAA

B7, B8

Power

Analog power

EXTCLK

Input

External input clock

VDD_SLVS

Power

0.3 V − 0.6 V or 1.7 V − 1.9 V port to HiSPi Output Driver. Set the

High_VCM (R0x306E[9]) bit to 1 when configuring VDD_SLVS to

1.7 V − 1.9 V

SLVS3_N

Output

HiSPi serial data, lane 3, differential N

SLVS3_P

Output

HiSPi serial data, lane 3, differential P

DGND

C5, D4, D5, E5, F5, G5, H5

Power

Digital ground

VDD

A6, A7, B6, C6, D6

Power

Digital power

AGND

C7, C8

Power

Analog ground

SADDR

Input

Two−Wire Serial address select. 0: 0x20, 1: 0x30

SCLK

Input

Two−Wire Serial clock input

SDATA

I/O

Two−Wire Serial data I/O

VAA_PIX

D7, D8

Power

Pixel power

LINE_VALID

Output

Asserted when DOUT line data is valid

FRAME_VALID

Output

Asserted when DOUT frame data is valid

PIXCLK

Output

Pixel clock out. DOUT is valid on rising edge of this clock

VDD_IO

E6, F6, G6, H6, H7

Power

I/O supply power

DOUT8

Output

Parallel pixel data output

DOUT9

Output

Parallel pixel data output

DOUT10

Output

Parallel pixel data output

DOUT11

Output

Parallel pixel data output (MSB)

TEST

Input.

Manufacturing test enable pin (connect to DGND)

DOUT4

Output

Parallel pixel data output

DOUT5

Output

Parallel pixel data output

DOUT6

Output

Parallel pixel data output

DOUT7

Output

Parallel pixel data output

TRIGGER

Input

Exposure synchronization input

OE_BAR

Input

Output enable (active LOW)

DOUT0

Output

Parallel pixel data output (LSB)

DOUT1

Output

Parallel pixel data output

DOUT2

Output

Parallel pixel data output

DOUT3

Output

Parallel pixel data output

RESET_BAR

Input

Asynchronous reset (active LOW). All settings are restored to factory

default

No connection

FLASH

Output

Flash control output

No connection

Reserved

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