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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AR0141CS датащи(PDF) 37 Page - ON Semiconductor |
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AR0141CS датащи(HTML) 37 Page - ON Semiconductor |
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37 / 48 page  AR0141CS www.onsemi.com 37 ELECTRICAL SPECIFICATIONS Unless otherwise stated, the following specifications apply under the following conditions: VDD = 1.8 V – 0.10 / +0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8 V ± 0.3 V; VDD_SLVS = 0.4 V – 0.1/+0.2; TA = −30°C to +85°C; output load = 10pF; frequency = 74.25 MHz; HiSPi off. Two−Wire Serial Register Interface The electrical characteristics of the two−wire serial register interface (SCLK, SDATA) are shown in Figure 44 and Table 18. Figure 44. Two-Wire Serial Bus Timing Parameters S Sr tSU;STO tSU;STA tHD;STA tHIGH tLOW tSU;DAT tHD;DAT tf SDATA SCLK P S tBUF tr tf tr tHD;STA Note: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Table 18. TWO−WIRE SERIAL BUS CHARACTERISTICS (fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; VDD_DAC = 2.8 V; TA = 25°C) Parameter Symbol Standard Mode Fast Mode Unit Min Max Min Max SCLK Clock Frequency fSCL 0 100 0 400 KHz Hold Time (Repeated) START Condition After this Period, the First Clock Pulse is Generated tHD;STA 4.0 − 0.6 − μs LOW Period of the SCLK Clock tLOW 4.7 − 1.3 − μs HIGH Period of the SCLK Clock tHIGH 4.0 − 0.6 − μs Set−up Time for a Repeated START Condition tSU;STA 4.7 − 0.6 − μS Data Hold Time tHD;DAT 0 (Note 4) 3.45 (Note 5) 0 (Note 6) 0.9 (Note 5) μs Data Set−up Time tSU;DAT 250 − 100 (Note 6) − ns Rise Time of both SDATA and SCLK Signals tr − 1000 20 + 0.1Cb (Note 7) 300 ns Fall Time of both SDATA and SCLK Signals tf − 300 20 + 0.1Cb (Note 7) 300 ns Set−up Time for STOP Condition tSU;STO 4.0 − 0.6 − μs Bus Free Time between a STOP and START Condition tBUF 4.7 − 1.3 − μs Capacitive Load for Each Bus Line Cb − 400 − 400 pF Serial Interface Input Pin Capacitance CIN_SI − 3.3 − 3.3 pF SDATA Max Load Capacitance CLOAD_SD − 30 − 30 pF SDATA Pull−up Resistor RSD 1.5 4.7 1.5 4.7 kΩ 1. This table is based on I2C standard (v2.1 January 2000). ON Semiconductor. 2. Two−wire control is I2C−compatible. 3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz. 4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 6. A Fast−mode I2C−bus device can be used in a Standard−mode I2C−bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard−mode I2C−bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. |
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