AR0141CS datasheet(15/48 Pages) ONSEMI

15 / 48 page

AR0141CS

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GAIN STAGES

The sensor analog gain stage will apply the same analog

gain to each color channel. Digital gain can be configured to

separate levels for each color channel.

The level of analog gain applied is controlled by the

coarse_gain and fine_gain at R0x3060 analog gain register.

The analog readout circuitry can be configured differently

for each analog gain level. Total analog gain is (2coarse_gain)

× (1 + fine_gain / 16), where coarse_gain = R0x3060[6:4],

fine_gain = R0x3060[3:0].

ON Semiconductor recommends limiting maximum analog

gain up to 12x gain for optimal image quality.

Each digital gain can be configured from a gain of 0 to

15.992 using R0x3056, R0x3058, R0x305A, R0x305C, and

R0x305E digital gain registers. The digital gain supports

128 gain steps per 6dB of gain. The format of each digital

gain register is “xxxx.yyyyyyy” where “xxxx” refers an

integer gain of 1 to 15 and “yyyyyyy” is a fractional gain

ranging from 0/128 to 127/128.

The sensor includes a digital dithering feature to reduce

quantization noise resulting from using digital gain. It can be

implemented by setting R0x30BA[5] to 1. The default value

is 0.

DATA PEDESTALS

The data pedestal is a constant offset that is added to pixel

values at the end of the datapath. The default offset is 168

and is a 12−bit offset. This offset matches the maximum

range used by the corrections in the digital readout path. The

purpose of the data pedestal is to convert negative values

generated by the digital datapath into positive output data.

RESET

The AR0141CS may be reset by the RESET_BAR pin

(active LOW) or the reset register.

Hard Reset of Logic

The host system can reset the image sensor by bringing the

RESET_BAR pin to a LOW state. Alternatively, the

RESET_BAR pin can be connected to an external RC circuit

for simplicity. Registers written via the two−wire interface

will not be preserved following a hard reset.

Soft Reset of Logic

Soft reset of logic is controlled by the R0x301A Reset

Furthermore, by asserting the soft reset, the sensor aborts the

current frame it is processing and starts a new frame. This bit

is a self−resetting bit and also returns to “0” during two−wire

serial interface reads.

CLOCKS

The AR0141CS requires one clock input (EXTCLK).

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