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CS43199 датащи(PDF) 24 Page - Cirrus Logic |
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CS43199 датащи(HTML) 24 Page - Cirrus Logic |
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24 / 111 page ![]() 24 DS1113F1 CS4399 4.3 Class H Output DSD_COPY_CHAN. Refer to Section 7.4.1–Section 7.4.7 for control register details. 4.3 Class H Output Fig. 4-2 shows the Class H operation. Figure 4-2. Class H Operation The CS4399 outputs use Cirrus Logic two-mode Class H technology. This prevents unnecessarily wasting energy during low power passages of program material or when the program material is played back at a low volume level. The internal charge pump is the central component of the two-mode Class H technology implemented in the CS4399. The charge pump receives its input voltage from the voltage present on the VCP or VP pin. From this input voltage, the charge pump creates the differential rail voltages supplied to the output stages.The charge pump can supply two sets of differential rail voltages: ±VCP and ±VP_LDO. HV_EN setting, as shown in Fig. 4-3, determines the VP_LDO voltage as shown in Table 4-1. HV_EN = 1 setting is required to support the 1.7-V full-scale voltage. In this setting, minimum VP is required to be higher than 3.3 V. When HV_ EN = 0, the max output voltage is 1.4-V RMS full-scale voltage. In this setting, minimum VP is required to be higher than 3V. Figure 4-3. Internal LDO Configuration Table 4-2 shows the nominal signal and volume level ranges when the output is set to the adapt modes explained in Section 4.3.1. If the signal level is greater than the maximum value of this range, then clipping can occur. Table 4-1. VP_LDO Voltage Per HV_EN Setting HV_EN VP_LDO Voltage 02.6 V 13.0 V Table 4-2. Class H Supply Modes Mode Class H Supply Level Signal 1 or Volume Level Range 2,3, 1.In adapt-to-signal, the volume level ranges are approximations but are within –0.5 dB from the values shown. 0 ±VP_LDO V, internally regulated from VP –11 dB 1 ±VCP < –11 dB VCP Class H Control VCP_FILT– –VCP –VP_LDO V VCP_FILT+ +VCP +VP_LDO V VP ADPT_PWR p. 89 VP VP_LDO Internal LDO HV_EN p. 89 |
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