CS43199 datasheet(77/111 Pages) CIRRUS

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DS1113F1

CS4399

7.3 ASP and XSP Registers

7.2.8

PLL Setting 8

Address 0x3001B

R/W

76543210

—

PLL_MODE

—

Default

00010011

Bits

Name

Description

7:2

—

Reserved

PLL_MODE

500/512 factor used in PLL frequency calculation equation, Eq. 4-1.

0 No bypass

1 (Default) Bypass

0—

Reserved

7.2.9

PLL Setting 9

Address 0x40002

R/W

76543210

—

PLL_REF_PREDIV

Default

00000010

Bits

Name

Description

7:2

—

Reserved

1:0

PLL_REF_

PREDIV

PLL reference divide select.

00 Divide by 1

01 Divide by 2

10 (Default) Divide by 4

11 Divide by 8

7.3.1

CLKOUT Control

Address 0x40004

R/W

76543210

—

CLKOUT_DIV

CLKOUT_SEL

Default

00000000

Bits

Name

Description

7:5

—

Reserved

4:2 CLKOUT_DIV Divider setting on internal MCLK path to CLKOUT.

000 (Default) Divide by 2

001 Divide by 3

010 Divide by 4

011 Divide by 8

100–111 Reserved

1:0 CLKOUT_SEL Select the source of CLKOUT.

00 (Default) XTAL/MCLK path

01 PLL output path

10–11 Reserved

7.3.2

ASP Numerator 1

Address 0x40010

R/W

76543210

ASP_N_LSB

Default

00000001

Bits

Name

Description

7:0

ASP_N_LSB The value in this register cannot be changed while the serial port is powered up.

ASP sample rate fractional divide numerator LSB. Along with ASP_M_MSB/LSB, selects the fractional divide value for

setting the SCLK frequency.

(Default) ASP_N = 1

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