CS43130 datasheet(43/137 Pages) CIRRUS

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DS1073F1

CS43130

4.9 Audio Serial Port (ASP)

• LRCKx—Toggles at external sample rate (Fsext). LRCK (left/right, I²S) identifies each channel’s (left or right)

location in the data word when I²S format is used. LRCK identifies the start of each serialized data word. FSYNC

(frame sync clock, TDM) identifies the start of each TDM frame.

• SDINx—Serial data input

4.9.4

High-Impedance Mode

Serial ports can be placed on a clock bus that allows multiple masters without the need for external buffers. xSP_3ST bits

place the internal buffers for the respective serial-port interface signals in a high-impedance state, allowing another device

to transmit clocks without bus contention. When the CS43130 serial port is a timing slave, its SCLK and LRCK I/Os are

always inputs and are thus unaffected by the xSP_3ST control. Fig. 4-19 shows the busing for CS43130 master timing

serial-port use case.

Figure 4-19. Serial Port Busing when Master Timed

4.9.5

Clock Generation and Control

The CS43130 has a flexible serial port clock generation subsystem that allows independent clocking of the two serial ports.

When operating as a master port, the serial port provides a bit clock (xSP_SCLK) and a left-right/frame sync signal (xSP_

LRCK/FSYNC).

Fig. 4-20 and Fig. 4-21 show the serial port clocking architecture.

Figure 4-20. xSP SCLK and MCLK Architecture

Note: x = XSP or ASP

Transmitting

Device #1 (DAC)

Transmitting

Device #2

x_SCLK,

x_LRCK

x_3ST

Receiving Device

Internal MCLK

N[13:0]

M[13:0]

SCLK

To LRCK

SCLK to

Serial Port

ASP_SCPOL_IN p. 102/

XSP_SCPOL_IN p. 104

ASP_M/SB p. 102/

XSP_M/SB p. 104

ASP_SCPOL_OUT p. 102/

XSP_SCPOL_OUT p. 104

ASP_M_LSB p. 100/XSP_M_LSB p. 103

ASP_M_MSB p. 101/XSP_M_MSB p. 103

ASP_N_LSB p. 100/XSP_N_LSB p. 102

ASP_N_MSB p. 100/XSP_N_MSB p. 103

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