CS43130 datasheet(49/137 Pages) CIRRUS

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DS1073F1

CS43130

4.9 Audio Serial Port (ASP)

4.9.9

Serial Port Status

Each serial port has five status bits. Each bit is sticky and must be read to be cleared. The status bits have associated

mask bits to mask setting the INT pin when the status bit sets. A brief description of each status bit is shown in Table 4-8.

4.9.10 Serial Port Clock Pin Status

There are various control bits available that affect the output state of the serial port clock and data pins. Table 4-9

summarizes the possible states depending on these bit settings.

4.9.11 DoP (DSD over PCM) Mode

DoP is a protocol for packetizing DSD data into a PCM frame for transmission over an existing I2S interface. The ASP or

XSP can accept DSD data in DoP format.

To use the DoP interface in Slave Mode, if MCLK_INT = 22.5792 MHz, the DoP interface clocks are required to be

synchronous to MCLK_INT.

Table 4-8. Serial Port Status

Name

Description

Request Overload Set when too many input buffers request processing at the same time. If all channel size

and location registers are properly configured to non-overlapping values, this error

status must never set.

ASP_OVFL_INT p. 115

XSP_OVFL_INT p. 116

LRCK Early

Set when the number of SCLK periods per LRCK phase (high or low) is less than the

expected count as determined by xSP_LCPR and xSP_LCHI.

Note: The Rx LRCK early interrupt status is set during the first receive LRCK early

event. Subsequent receive LRCK early events are not indicated until after valid LRCK

transitions are detected.

ASP_EARLY_INT p. 116

XSP_EARLY_INT p. 116

LRCK Late

Set when the number of SCLK periods per LRCK phase (high or low) is greater than the

expected count as determined by xSP_LCPR and xSP_LCHI.

ASP_LATE_INT p. 116

XSP_LATE_INT p. 116

LRCK Error

Logical OR of LRCK early and LRCK late.

ASP_ERROR_INT p. 116

XSP_ERROR_INT p. 116

No LRCK

Set when the number of SCLK periods counted exceeds twice the value of LRCK period

(xSP_LCPR) without an LRCK edge.

The Tx No LRCK interrupt status is set during the first instance of a no transmit LRCK

condition. Subsequent no transmit LRCK conditions are not indicated until after valid

LRCK transitions are detected.

ASP_NOLRCK_INT p. 116

XSP_NOLRCK_INT p. 116

Table 4-9. xSP_SCLK and xSP_LRCK/FSYNC Pin States

xSP_3ST

xSP_M/S

PDN_xSP

xSP_SCLK

Pin State

xSP_LRCK/FSYNC

Pin State

Hi-Z with weak pull-down

Active

Inactive

Inactive 1

1.If xSP_LCPOL_OUT is set, xSP_LRCK/FSYNC inactive output is high. If xSP_LCPOL_OUT is cleared, xSP_LRCK/FSYNC

inactive output is low.

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