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CS43130 датащи(PDF) 91 Page - Cirrus Logic

номер детали CS43130
подробное описание детали  130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver
PDF  137 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43130 датащи(HTML) 91 Page - Cirrus Logic

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DS1073F1
91
CS43130
6 Register Quick Reference
6 Register Quick Reference
Notes: Default values are shown below the bit field names. The default values in all reserved bits must be preserved.
Table 6-1. Register Quick Reference
Address
Function
7
654321
0
0x01 0000 Device ID A and B
(Read Only)
DEVIDA
DEVIDB
p. 95
0
100001
1
0x01 0001 Device ID C and D
(Read Only)
DEVIDC
DEVIDD
p. 95
0
001001
1
0x01 0002 Device ID E (Read
Only)
DEVIDE
—
p. 95
0
000000
0
0x01 0004 Revision ID (Read
Only)
AREVID
MTLREVID
p. 95
xxx
xxxxx
0x01 0005 Subrevision ID (Read
Only)
SUBREVID
p. 95
x
x
x
x
x
x
x
x
0x01 0006 System Clocking
Control
—
MCLK_INT
MCLK_SRC_SEL
p. 96
0
000011
0
0x01 0007–
0x01 000A
Reserved
—
0
000000
0
0x01 000B Serial Port Sample
Rate
—ASP_SPRATE
p. 96
0
000000
1
0x01 000C Serial Port Sample Bit
Size
—
XSP_SPSIZE
ASP_SPSIZE
p. 96
0
000010
1
0x01 000D Pad Interface
Configuration
—
XSP_3ST
ASP_3ST
p. 96
0
000001
1
0x01 000E–
0x01 FFFF
Reserved
—
0
000000
0
0x02 0000 Power Down Control
PDN_XSP
PDN_ASP
PDN_DSDIF
PDN_HP
PDN_XTAL
PDN_PLL
PDN_CLKOUT
—
p. 97
1
111111
0
0x02 0001–
0x02 0051
Reserved
—
0
000000
0
0x02 0052 Crystal Setting
—
XTAL_IBIAS
p. 97
00
0
0
0
1
0
0
0x02 0053–
0x03 0000
Reserved
—
0
000000
0
0x03 0001 PLL Setting 1
—
PLL_START
p. 98
0
000000
0
0x03 0002 PLL Setting 2
PLL_DIV_FRAC_0
p. 98
0
000000
0
0x03 0003 PLL Setting 3
PLL_DIV_FRAC_1
p. 98
0
000000
0
0x03 0004 PLL Setting 4
PLL_DIV_FRAC_2
p. 98
0
000000
0
0x03 0005 PLL Setting 5
PLL_DIV_INT
p. 98
0
100000
0
0x03 0006–
0x03 0007
Reserved
—
0
000000
0
0x03 0008 PLL Setting 6
PLL_OUT_DIV
p. 99
0
001000
0
0x03 0009 Reserved
—
0
000000
0
0x03 000A PLL Setting 7
PLL_CAL_RATIO
p. 99
1
000000
0
0x03 000B–
0x03 001A
Reserved
—
0
000000
0
0x03 001B PLL Setting 8
—
—
—
PLL_MODE
—
p. 99
0
000001
1
0x03 001C–
0x04 0001
Reserved
—
0
000000
0
0x04 0002 PLL Setting 9
—
PLL_REF_PREDIV
p. 99
0
000001
0
0x04 0003 Reserved
—
0
000000
0



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