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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS43130 датащи(PDF) 40 Page - Cirrus Logic |
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CS43130 датащи(HTML) 40 Page - Cirrus Logic |
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40 / 137 page  40 DS1073F1 CS43130 4.7 Clock Output and Fractional-N PLL 4.7.2 Fractional-N PLL Internal Interface Fig. 4-18 shows how PLL operation can be configured. Figure 4-18. Fractional-N PLL Use Eq. 4-1 to calculate the PLL output frequency. Equation 4-1. PLL Output Frequency Equation PLL_REF source must be in range below: Table 4-4 lists common settings with XTAL input as PLL reference. Table 4-5 lists common settings with MCLK input as PLL reference. PLL_REF Source PLL_REF_PREDIV Input Minimum Maximum MCLK/XIN pin 9.6 MHz 26 MHz Table 4-4. PLL Configuration for Typical Use Case (XTAL as the PLL Reference) XTAL (MHz) PLL_REF_PREDIV (Divide-by Value) PLL_REF_PREDIV (Setting) PLL_ DIV_INT PLL_DIV_FRAC PLL_OUT_DIV PLL_ MODE PLL OUT (MHz) PLL_CAL_ RATIO 22.5792 8 0x3 0x44 0x06 F700 0x08 0 24.576 139 24.576 8 0x3 0x49 0x80 0000 0x0A 1 22.5792 118 Table 4-5. PLL Configuration for Typical Use Case (XIN/MCLK as the PLL Reference) XIN/MCLK (MHz) PLL_REF_PREDIV (Divide-by Value) PLL_REF_PREDIV (Setting) PLL_DIV_INT PLL_DIV_FRAC PLL_OUT_DIV PLL_ MODE PLL_OUT (MHz) PLL_CAL_ RATIO 11.2896 4 0x2 0x40 0x00 0000 0x08 1 22.5792 128 40x2 0x44 0x06 F700 0x08 0 24.576 139 22.5792 8 0x3 0x44 0x06 F700 0x08 0 24.576 139 12.000 4 0x2 0x49 0x80 0000 0x0A 0 22.5792 120 40x2 0x40 0x00 0000 0x08 0 24.576 131 24.000 8 0x3 0x49 0x80 0000 0x0A 0 22.5792 120 8 0x3 0x40 0x00 0000 0x08 0 24.576 131 12.288 4 0x2 0x49 0x80 0000 0x0A 1 22.5792 118 40x2 0x40 0x00 0000 0x08 1 24.576 128 24.576 8 0x3 0x49 0x80 0000 0x0A 1 22.5792 118 9.600 4 0x2 0x49 0x80 0000 0x08 0 22.5792 151 40x2 0x50 0x00 0000 0x08 0 24.576 164 PLL XTI/MCLK PLL_OUT PLL_DIV_INT p. 98 PLL_DIV_FRAC_0 p. 98 PLL_DIV_FRAC_1 p. 98 PLL_DIV_FRAC_2 p. 98 PLL_MODE p. 99 PLL_REF_ PREDIV p. 99 PDN_PLL p. 97 PLL_START p. 98 PLL_OUT_ DIV p. 99 PLL_OUT = PLL_REF PLL_REF_PREDIV × 1 PLL_OUT_DIV PLL_DIV_INT + PLL_DIV_FRAC or 1, selected by PLL_Mode × 500 512 |
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