CS35L32 datasheet(25/51 Pages) CIRRUS

25 / 51 page

DS963F5

CS35L32

4.11 Audio/Data Serial Port (ADSP)

4.11.1.1 Tristating the ADSP SDOUT Path (SDOUT_3ST)

If the SDOUT functionality of the ADSP is not required, power losses caused by the charging and discharging of parasitic

capacitances on this pin can be eliminated by setting SDOUT_3ST, so that the SDOUT line is tristated. When reactivating

SDOUT, the associated circuits come alive and a full LRCK cycle elapses before SDOUT data is valid.

4.11.2 Master and Slave Timing

The serial port operates as either the master of timing or the slave to another device’s timing. When the serial port is

master, SCLK and LRCK are outputs; when it is a slave, they are inputs. Master/Slave Mode is configured by the M/S bit.

In I²S Master Mode, the SCLK and LRCK clock outputs are derived from MCLKINT. SCLK is generated to have

approximately 64 cycles per LRCK cycle.

In Slave Mode, because there is no sample-rate conversion from the serial port to the device core, the serial port audio

sample rate (fLRCK) must equal the core sample rate (Fs). To ensure that the CS35L32 maintains synchronization with the

serial port sample rate, the RATIO divider (see p. 37) is programmed to indicate the sample rate to MCLKINT relationship.

Table 4-7 shows the corresponding RATIO (fMCLK(INT)⁄fLRCK) for each MCLKINT at the supported LRCK rate. In Master

Mode, in a dual-CS35L32 configuration (see Section 4.12.3) with MCLKINT = 6 MHz, a ratio of 125 is not supported.

ADSPCLK_ERR (see p. 41) indicates when the ADSP attempts to resynchronize due to the absence of an LRCK edge at

the expected time due to excessive jitter, misprogramming, or clock absence. Note that, given that the clock-checking

circuit checks for LRCK edges appearing in the expected location relative to internal timing, if the LRCK frequency is an

integer multiple of the expected rate (e.g., the LRCK rate is 96 kHz [2 x 48 kHz] vs. the expected 48 kHz), ADSPCLK_ERR

does not detect this error condition. Also note that, since the clock-checking circuit monitors edges, if LRCK is removed

and no further clock edges are produced, ADSPCLK_ERR triggers only once while the LRCK is removed.

Table 4-7 lists supported serial-port audio sample rates, their relationship to the MCLKINT rate, and the programming

required to generate a given LRCK rate in Master Mode and ensure the serial port maintains synchronization in Slave

Mode.

If all amplifier functionality is not being used, but CS35L32 clock mastering is desired, set up the clocks using the clocking

control register controls, then set SDOUT_3ST. In this scenario, since the amplifier is inaccessible, it should be powered

down to save power (PDN_AMP = 1).

4.11.3 ADSP in I2S Mode

The ADSP operates in traditional I²S format, with a minor modification. On the transmit side, the data structure is modified

to transmit nonconventional data (e.g., the monitored signals) in a compatible format. Receive Mode is not supported.

4.11.3.1 Data Bit Depths

The data word length of the I²S interface format is ambiguous. Fortunately, the I²S format is also left justified, with a MSB-

to-LSB bit ordering, which negates the need for a word-length control register. The following text describes how different

bit depths are handled with the I²S format.

Table 4-6. ADSP Operational Mode and Pin Configurations

M/S SDOUT_3ST ADSP Operational Mode SDOUT Pin Driver LRCK Pin Driver SCLK Pin Driver

I2S Slave Mode

Output

Input

I2S Slave Mode

Hi-Z

Input

I2S Master Mode

Output

I2S Master Mode

Hi-Z

Output

Table 4-7. ADSP Rates

MCLKINT Rate

(MHz)

LRCK Rate

(kHz)

fMCLK(INT)/fLRCK

(Rate Ratio)

RATIO

6.0000

48.000

125

6.1440

48.000

128

CS35L32 датащи(PDF) 25 Page - Cirrus Logic

CS35L32 датащи(HTML) 25 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

датащи скачать

ссылки URL