CS35L32 datasheet(14/51 Pages) CIRRUS

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DS963F5

CS35L32

3 Characteristics and Specifications

Table 3-13. Switching Specifications: I²C Control Port

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, TA = +25°C, Inputs: Logic 0 = GNDA = GNDP = 0 V, Logic 1 =

VA; SDA load capacitance equal to maximum value of CB specified below; minimum SDA pull-up resistance, RP(min).1 Section 9 describes some

parameters in detail. All specifications are valid for the signals at the pins of the CS35L32 with the specified load capacitance; input timings are measured

at VIL and VIH thresholds; output timings are measured at VOL and VOH thresholds (see Table 3-8).

1.The minimum RP and RP_I values (resistors shown in Fig. 2-1) are determined using the maximum level of VA, the minimum sink current strength of

their respective output, and the maximum low-level output voltage VOL(specified in Table 3-8). The maximum RP and RP_I values may be determined

by how fast their associated signals must transition (e.g., the lower the value of RP, the faster the I2C bus is able to operate for a given bus load

capacitance). See the I²C switching specifications in Table 3-13 and the I²C bus specification referenced in Section 13.

Parameter

Symbol 2

2.I²C control-port timing.

Min

Max

Units

RESET rising edge to start

tIRS

500

—

SCL clock frequency

fSCL

—

400

kHz

Start condition hold time (before first clock pulse)

tHDST

0.6

—

µs

Clock low time

tLOW

1.3

—

µs

Clock high time

tHIGH

0.6

—

µs

Setup time for repeated start condition

tSUST

0.6

—

µs

SDA input hold time from SCL falling 3

3.Data must be held long enough to bridge the transition time, tF, of SCL.

tHDDI

00.9

µs

SDA output hold time from SCL falling

tHDDO

0.2

0.9

µs

SDA setup time to SCL rising

tSUD

100

—

Rise time of SCL and SDA

tRC

—

300

Fall time of SCL and SDA

tFC

—

300

Setup time for stop condition

tSUSP

0.6

—

µs

Bus free time between transmissions

tBUF

1.3

—

µs

SDA bus capacitance

—

400

tBUF

tLOW

Stop

Start

Stop

Repeated

SDA

SCL

tIRS

RESET

tHDDI,

tHDDO

tSUD

tSUST

tRC

tHDST

tHIGH

tHDST

tFC

tSUSP

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