AD9286BCPZ-500 datasheet(27/28 Pages) AD

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AD9286

Data Sheet

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the AD9286 as a system,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements that are needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9286, it is strongly recom-

mended that two separate supplies be used. Use one 1.8 V supply

for analog (AVDD); use a separate 1.8 V supply for the digital

output supply (DRVDD). If a common 1.8 V AVDD and DRVDD

supply must be used, the AVDD and DRVDD domains must be

isolated with a ferrite bead or filter choke and separate decoupling

capacitors. Several different decoupling capacitors can be used

to cover both high and low frequencies. Locate these capacitors

close to the point of entry at the printed circuit board (PCB)

level and close to the pins of the part, with minimal trace length.

A single PCB ground plane should be sufficient when using the

AD9286. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

Exposed Paddle Thermal Heat Sink Recommendations

The exposed paddle (Pin 0) is the only ground connection

for the AD9286; therefore, it must be connected to analog

ground (AGND) on the customer PCB. To achieve the best

electrical and thermal performance, mate an exposed (no

solder mask), continuous copper plane on the PCB to the

AD9286 exposed paddle, Pin 0.

The copper plane should have several vias to achieve the

lowest possible resistive thermal path for heat dissipation

to flow through the bottom of the PCB. Fill or plug these

vias with nonconductive epoxy.

To maximize the coverage and adhesion between the ADC and

the PCB, a silkscreen should be overlaid to partition the continuous

plane on the PCB into several uniform sections. This provides

several tie points between the ADC and the PCB during the reflow

process. Using one continuous plane with no partitions guarantees

only one tie point between the ADC and the PCB. For detailed

information about packaging and PCB layout of chip scale

packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP), at www.analog.com.

VCM

The VCM pin should be decoupled to ground with a 0.1 µF

capacitor.

RBIAS

The AD9286 requires that a 10 kΩ resistor be placed between

the RBIAS pin and ground. This resistor, which sets the master

current reference of the ADC core, should have at least a 1%

tolerance.

Reference Decoupling

Decouple the VREF pin externally to ground with a low ESR,

1.0 µF capacitor in parallel with a low ESR, 0.1 µF ceramic

capacitor.

SPI Port

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9286 to prevent these signals from transitioning at the converter

inputs during critical sampling periods.

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