AD9286

Data Sheet

Rev. C | Page 6 of 27

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.

Table 4.

Parameter

Temperature

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

60

500

MHz

Full

2

Ns

Full

1

Ns

DATA OUTPUT PARAMETERS

3.7

ns

Full

3.7

ns

Full

−280

−60

100

ps

Pipeline Delay (Latency)

Full

11

Cycles

Full

1.0

ns

Full

0.1

ps rms

Full

500

μs

OUT-OF-RANGE RECOVERY TIME

Full

4

Cycles

SPI TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Min

Typ

Max

Unit

SPI TIMING REQUIREMENTS

Setup time between the data and the rising edge of SCLK

2

ns

Hold time between the data and the rising edge of SCLK

2

ns

Period of the SCLK

40

ns

Setup time between CSB and SCLK

2

ns

Hold time between CSB and SCLK

2

ns

SCLK pulse width high

10

ns

SCLK pulse width low

10

ns

Time required for the SDIO pin to switch from an input

to an output relative to the SCLK falling edge

10

ns

Time required for the SDIO pin to switch from an output

to an input relative to the SCLK rising edge

10

ns

Timing Diagrams

N – 1

N – 2

N + 1

M – 11 N – 11 M – 10 N – 10 M – 9

N – 9

M – 8

M – 7

N – 8

N + 2

N + 4

N + 3

N

M + 5

M + 4

M + 3

M + 1

M + 2

M

M – 1

VIN1+, VIN1–

VIN2+, VIN2–

CLK+

CLK–

DCO+, DCO–

DATA

Figure 2. Output Timing Diagram, Sample Mode = Interleaved (Default)