AD9286BCPZ-500 datasheet(18/28 Pages) AD

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Data Sheet

AD9286

In this mode, the AD9286 can also function as a dual 8-bit,

250 MSPS converter. This may be useful in applications where

both a single 8-bit, 500 MSPS and a dual 8-bit, 250 MSPS converter

are needed. The clock management block requires that CLK±

and AUXCLK± be either 0° or 180°, relative to each other. If this

requirement is satisfied, the circuit correctly time aligns the data

coming out of each ADC core.

If the user desires to operate the AD9286 as a dual 8-bit, 250

MSPS converter and supply only a single clock, this is achieved

by setting sample mode to simultaneous, with the AUXCLKEN

pin tied to AGND. In this mode, the two ADC cores sample

simultaneously. For a summary of all supported clocking

modes, see Table 9.

The AD9286 supports the clocking of each internal ADC with

separate clocks. By setting AUXCLKEN to DRVDD, the user

can supply a differential auxiliary clock to AUXCLK+ and

AUXCLK−. In this mode, each internal ADC core has a maximum

sample rate of 250 MSPS. This mode bypasses the internal timing

adjustment blocks.

Interleave Performance

The AD9286 achieves 500 MSPS conversion by time interleaving

two 250 MSPS ADC channels. Although this technique is sufficient

in achieving 8-bit performance, quantifiable errors are introduced.

These errors come from three sources: gain mismatch, imperfect

out-of-phase sampling, and offset mismatch between the two

channels. Distortion appears spectrally in two distinct ways: gain

and timing mismatch appear as an alias spur (see Equation 1), and

offset mismatch appears as a spur located at the Nyquist rate of the

converter (see Equation 2).

fALIAS_SPUR = fS/2 − fIN

(1)

where:

fS is the interleaved sample rate.

fIN is the analog input frequency.

fOFFSET_SPUR = fS/2

(2)

where fS is the interleaved sample rate.

The magnitude of the alias spur (AS) contributed by a gain error

is shown in Equation 3.

ASGAIN (dBc) = 20 × log(ASGAIN) = 20 × log(GE/2)

(3)

where:

GE = Gain_Error_Ratio = 1 − VFS1/VFS2.

VFSn is the full-scale voltage of Core n.

ASGAIN, as a function of gain mismatch, is shown in Figure 30.

0.5

0.4

0.3

0.2

0.1

GAIN MISMATCH (% FS)

Figure 30. ASGAIN as a Function of Gain Mismatch

The magnitude of the alias spur (AS) contributed by a timing

error is shown in Equation 4.

ASTIMING (dBc) = 20 × log(ASTIMING) = 20 × log(θEP/2)

(4)

where θEP = ωA × ∆tE(Radians), with ωA as the analog input

frequency and ∆tE as the clock skew error.

ASTIMING, as a function of timing error, is shown in Figure 31.

TIMING ERROR (ps)

Figure 31. ASTIMING as a Function of Timing Error

The total magnitude of the alias spur (AS) is shown in Equation 5.

ASTOTAL (dB) = 20 × log√((ASGAIN)2 + (ASTIMING)2)

(5)

Table 9. Supported Clocking Modes

Effective Number

of Channels

Maximum CLK

Frequency

AUXCLK

Frequency

AUXCLK Phase

Relative to CLK

AUXCLKEN

SPI Register,

Address 0x09, Bit 3

Clock Timing Adjust

One

500 MSPS

N/A

Low

Internal

Two

250 MSPS

N/A

Low

N/A

Two

250 MSPS

CLK

0°

High

N/A

One

250 MSPS

CLK

180°

High

External

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