AD9286BCPZ-500 datasheet(23/28 Pages) AD

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AD9286

Data Sheet

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table (see Table 13) has

eight bit locations. The memory map is roughly divided into

three sections: the chip configuration registers (Address 0x00

to Address 0x02), the device index and transfer registers

(Address 0x05 and Address 0xFF), and the program registers

(Address 0x08 to Address 0x38).

Table 13 documents the default hexadecimal value for each

hexadecimal address shown. The column with the heading Bit 7

(MSB) is the start of the default hexadecimal value given. For

more information on this function and others, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI. This

document details the functions controlled by Register 0x00 to

Open Locations

All address and bit locations that are not included in the SPI

map are not currently supported for this device. Unused bits of

a valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open. If the entire address location is open, it is omitted from the

SPI map (for example, Address 0x13) and should not be written.

Default Values

After the AD9286 is reset, critical registers are loaded with

default values. The default values for the registers are given

in the memory map register table (see Table 13).

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Bit is cleared” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 to Address 0x38 are shadowed. Writes to these

addresses do not affect part operation until a transfer command

is issued by writing 0x01 to Address 0xFF, setting the transfer bit.

Setting the transfer bit allows these registers to be updated

internally and simultaneously. The internal update takes place

when the transfer bit is set, and then the bit autoclears.

Channel-Specific Registers

Some channel setup functions can be programmed differently

for each channel. In these cases, channel address locations are

internally duplicated for each channel. These registers and bits

are designated in the memory map register table as local. These

local registers and bits can be accessed by setting the appropriate

Channel 1 (Bit 0) or Channel 2 (Bit 1) bits in Register 0x05.

If both bits are set, the subsequent write affects the registers of

both channels. In a read cycle, set only Channel 1 or Channel 2

to read one of the two registers. If both bits are set during an SPI

read cycle, the part returns the value for Channel 1. Registers and

bits designated as global in the memory map register table affect

the entire part or the channel features for which independent

settings are not allowed between channels. The settings in

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