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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSM2190F4V датащи(PDF) 48 Page - STMicroelectronics |
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DSM2190F4V датащи(HTML) 48 Page - STMicroelectronics |
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48 / 61 page  DSM2190F4 48/61 Table 28. CPLD Macrocell Synchronous Clock Mode Timing Note: 1. Fast Slew Rate output available on PB3-PB0, and PD2-PD0. 2. CLKIN (PD1) tCLCL = tCH + tCL . Table 29. CPLD Macrocell Asynchronous Clock Mode Timing Symbol Parameter Conditions -15 PT Aloc Turbo Off Slew Rate1 Unit Min Max fMAX Maximum Frequency External Feedback 1/(tS+tCO) 18.8 MHz Maximum Frequency Internal Feedback (fCNT) 1/(tS+tCO–10) 23.2 MHz Maximum Frequency Pipelined Data 1/(tCH+tCL) 33.3 MHz tS Input Setup Time 25 Add 4 Add 20 ns tH Input Hold Time 0 ns tCH Clock High Time Clock Input 15 ns tCL Clock Low Time Clock Input 15 ns tCO Clock to Output Delay Clock Input 28 Sub 6 ns tARD CPLD Array Delay Any Macrocell 29 Add 4 ns tMIN Minimum Clock Period2 tCH+tCL 29 ns Symbol Parameter Conditions -15 PT Aloc Turbo Off Slew Rate Unit Min Max fMAXA Maximum Frequency External Feedback 1/(tSA+tCOA) 19.2 MHz Maximum Frequency Internal Feedback (fCNTA) 1/(tSA+tCOA–10) 23.8 MHz Maximum Frequency Pipelined Data 1/(tCHA+tCLA) 27 MHz tSA Input Setup Time 12 Add 4 Add 20 ns tHA Input Hold Time 15 ns tCHA Clock High Time 22 Add 20 ns tCLA Clock Low Time 15 Add 20 ns tCOA Clock to Output Delay 40 Add 20 Sub 6 ns tARD CPLD Array Delay Any Macrocell 29 Add 4 ns tMINA Minimum Clock Period 1/fCNTA 42 ns |
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