DSM2190F4V datasheet(40/61 Pages) STMICROELECTRONICS

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DSM2190F4

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PROGRAMMING IN-CIRCUIT USING JTAG ISP

In-System Programming (ISP) can be performed

through the JTAG signals on Port C. This serial in-

terface allows programming of the entire DSM de-

vice or subsections (i.e. only Flash memory but not

the PLDs) without and participation of the DSP. A

blank DSM device soldered to a circuit board can

be completely programmed in 10 to 25 seconds.

The basic JTAG signals; TMS, TCK, TDI, and

TDO form the IEEE-1149.1 interface. The DSM

device does not implement the IEEE-1149.1

Boundary Scan functions. The DSM uses the

JTAG interface for ISP only. However, the DSM

device can reside in a standard JTAG chain with

other JTAG devices as it will remain in BYPASS

mode while other devices perform Boundary

Scan.

ISP programming time can be reduced as much as

30% by using two more signals on Port C, TSTAT

and TERR in addition to TMS, TCK, TDI and TDO.

See Table 20. The FlashLINKTM JTAG program-

ming cable available from STMicroelectronics for

$59USD and PSDsoft Express software that is

available at no charge from

www.st.com/psm is all

that is needed to program a DSM device using the

parallel port on any PC or laptop.

By default, the four pins on Port C are enabled for

the basic JTAG signals TMS, TCK, TDI, and TDO

on a blank device (and as shipped from factory)

See Application Note

AN1153 for more details on

JTAG In-System Programming (ISP).

Standard JTAG Signals. The

standard

JTAG

signals (TMS, TCK, TDI, and TDO) can be en-

abled by any of three different conditions that are

logically ORed.

The following symbolic logic equation specifies the

conditions enabling the four basic JTAG signals

(TMS, TCK, TDI, and TDO) on their respective

Port C pins. For purposes of discussion, the logic

label JTAG_ON is used. When JTAG_ON is true,

the four pins are enabled for JTAG operation.

When JTAG_ON is false, the four pins can be

used for general device I/O as specified in PSD-

soft Express. JTAG_ON can become true by any

of three different ways as shown:

JTAG_ON =

1. PSDsoft Express Pin Configuration -OR-

2. PSDsoft Express PLD equation -OR-

3. DSP writes to register in

csiop block

Method 1 is most common. This is when the JTAG

pins are selected in PSDsoft Express to be “dedi-

cated” JTAG pins. They can always transmit and

receive JTAG information because they are “full-

time” JTAG pins.

Method 2 is used only when the JTAG pins are

multiplexed with general I/O functions. For de-

signs that need every I/O pin, the JTAG pins may

be used for general I/O when they are not used for

ISP. However, when JTAG pins are multiplexed

with general I/O functions, the designer must in-

clude a way to get the pins back into JTAG mode

when it is time for JTAG operations again. In this

case, a single PLD input from Ports B, C, or D

must be dedicated to switch the Port C pins from I/

O mode back to ISP mode at any time. It is recom-

mended to physically connect this dedicated PLD

input pin to the JEN\ output signal from the

Flashlink cable when multiplexing JTAG signals.

See Application Note

AN1153 for details.

Method 3 is rarely used to control JTAG pin oper-

ation. The DSP can set the port C pins to function

as JTAG ISP by setting the JTAG Enable bit in a

csiop block, but as soon as the DSM

chip is reset, the csiop block registers are cleared,

which turns off the JTAG-ISP function. Controlling

JTAG pins using this method is not recommended.

Table 20. JTAG Port Signals

JTAG Extensions. TSTAT and TERR are two

JTAG extension signals (must be used as a pair)

enabled by a command received over the four

standard JTAG signals (TMS, TCK, TDI, and

TDO) by PSDsoft Express. They are used to

speed Program and Erase cycles by indicating

status on device pins instead of having to scan the

status out serially using the standard JTAG chan-

nel. See Application Note

AN1153.

TERR indicates if an error has occurred when

erasing a sector or programming a byte in Flash

memory. This signal goes Low (active) when an

Error condition occurs.

TSTAT behaves the same as Ready/Busy de-

scribed previously. TSTAT is inactive logic 1 when

the device is in Read mode (Flash memory con-

tents can be read). TSTAT is logic 0 when Flash

memory Program or Erase cycles are in progress.

TSTAT and TERR can be configured as open-

drain type signals with PSDsoft Express. This fa-

cilitates a wired-OR connection of TSTAT signals

Port C Pin

JTAG Signals

Description

PC0

TMS

Mode Select

PC1

TCK

Clock

PC3

TSTAT

Status

PC4

TERR

Error Flag

PC5

TDI

Serial Data In

PC6

TDO

Serial Data Out

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