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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSM2190F4V датащи(PDF) 25 Page - STMicroelectronics |
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DSM2190F4V датащи(HTML) 25 Page - STMicroelectronics |
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25 / 61 page  25/61 DSM2190F4 DECODE PLD (DPLD) The DPLD, shown in Figure 14, is used for decod- ing the address for internal and external compo- nents. The DPLD can be used to generate the following decode signals: s 8 Main Flash memory Sector Select ( FS0-FS7) signals with three product terms each s 4 Secondary Flash memory Sector Select ( CSBOOT0-CSBOOT3) signals with three product terms each s 1 internal csiop select for DSM device control and status registers ( csiop is the base address of the block of 256 byte locations) s 1 JTAG Select signal (enables JTAG operations on Port C when multiplexing JTAG signals with general I/O signals) s 3 external chip select output signals for Port D pins, each with one product term. Figure 14. DPLD Logic Array (INPUTS) (16) (8) (16) (3) CNTRL[2:0] (Read/Write Control Signals) I/O PORTS (PORT A,B,C) (8) PG0-PG7 (8) MCELLAB.FB [7:0] (Feedback) MCELLBC.FB [7:0] (Feedback) A[15:0] (3) (1) PD[2:0] RESET (1) RD_BSY CSIOP JTAGSEL ECS0 ECS1 8 Flash Main Memory Sector Selects I/O Decoder Select JTAG ISP FS0 FS7 3 3 3 3 3 3 3 3 1 ECS2 FS1 FS2 FS3 FS6 FS5 FS4 1 1 1 1 External Chip Selects to PORT D CSBOOT0 CSBOOT1 CSBOOT2 CSBOOT3 4 Secondary Flash Memory Sector Selects 3 3 3 3 AI04958 |
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