DSM2190F4V datasheet(39/61 Pages) STMICROELECTRONICS

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DSM2190F4

Figure 24. Reset (RESET) Timing

Power On Reset, Warm Reset, Power-down

Power On Reset. Upon Power-up, the device re-

quires a Reset (RESET) pulse of duration tNLNH-PO

after VCC is steady. During this time period, the de-

vice loads internal configurations, clears some of

the registers and sets the Flash memory into Op-

erating mode. After the rising edge of Reset (RE-

SET

), the device remains in the Reset mode for an

additional period, tOPR, before the first memory ac-

cess is allowed.

The Flash memory is reset to the Read Array

mode upon Power-up. Sector Select FS0-FS7

must all be Low, Write Strobe (WR, CNTL0) High,

during Power On Reset for maximum security of

the data contents and to remove the possibility of

a byte being written on the first edge of Write

Strobe (WR, CNTL0). Any Flash memory Write cy-

cle initiation is prevented automatically when VCC

is below VLKO.

Table 19. Status During Power-On Reset, Warm Reset and Power-down Mode

Warm Reset. Once the device is up and running,

the device can be reset with a pulse of a much

shorter duration, tNLNH. The same tOPR period is

needed before the device is operational after

warm reset. Figure 24 shows the timing of the

Power-up and warm reset.

I/O Pin, Register and PLD Status at Reset. Ta-

ble 19 shows the I/O pin, register and PLD status

during Power On Reset, warm reset and Power-

down mode. PLD outputs are always valid during

warm reset, and they are valid in Power On Reset

once the internal device Configuration bits are

loaded. This loading of the device is completed

typically long before the VCC ramps up to operat-

ing level. Once the PLD is active, the state of the

outputs are determined by the PSDsoft Express

equations.

tNLNH-PO

tOPR

AI02866b

RESET

tNLNH

tNLNH-A

tOPR

VCC

CC(min)

Power-On Reset

Warm Reset

Port Configuration

Power-On Reset

Warm Reset

Power-down Mode

MCU I/O

Input mode

Unchanged

PLD Output

Valid after internal PSD

configuration bits are

loaded

Valid

Depends on inputs to PLD

(addresses are blocked in

PD mode)

Power-On Reset

Warm Reset

Power-down Mode

PMMR0 and PMMR2

Cleared to 0

Unchanged

OMC Flip-flop status

Cleared to 0 by internal

Power-On Reset

Depends on .re and .pr

equations

Depends on .re and .pr

equations

All other registers

Cleared to 0

Unchanged

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