DSM2190F4V datasheet(7/61 Pages) STMICROELECTRONICS

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DSM2190F4

Figure 5. Block Diagram

OMCs: The general structure of the CPLD is simi-

lar in nature to a 22V10 PLD device with the famil-

iar sum-of-products (AND-OR) construct. True

and compliment versions of 64 input signals are

available to a large AND array. AND array outputs

feed into a multiple product-term OR gate within

each OMC (up to 10 product-terms for each

OMC). Logic output of the OR gate can be passed

on as combinatorial logic or combined with a flip-

flop within in each OMC to realize sequential logic.

OMCs can be used as a buried nodes with feed-

back to the AND array or OMC output can be rout-

ed to pins on Port B or PortC.

IMCs: Inputs from pins on Port B or Port C are

routed to IMCs for conditioning (clocking or latch-

ing) as they enter the chip, which is good for sam-

pling and debouncing inputs. Alternatively, IMCs

can pass Port input signals directly to PLD inputs

without clocking or latching. The DSP may read

the IMCs at any time.

Runtime Control Registers

A block of 256 bytes is decoded inside the DSM

device as DSM control and status registers. 27

registers are used in the block of 256 locations to

control the output state of I/O pins, to read I/O

pins, to control power management, to read/write

macrocells, and other functions at runtime. See

Table 4 for description. The base address of these

256 locations is referred to in this data sheet as

csiop (Chip Select I/O Port). Individual registers

within this block are accessed with an offset from

the base address. The DSP accesses

csiop regis-

ters using I/O memory with the IOMS strobe.

csiop

registers are accessed as bytes.

Memory Page Register

This 8-bit register can be loaded and read by the

DSP at runtime as one of the

csiop registers. Its

outputs feed directly into the PLDs. The page reg-

ister can be used for special memory mapping re-

quirements and also for general logic.

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

I/O PORT

PC0

PC1

PC3

PC4

PC5

PC6

I/O PORT

COMPLEX PLD

(CPLD)

16 Input

Macrocell

16 Output Macrocells

PAGE REG

SECURITY

LOCK

ALLO-

CATOR

PIN FEEDBACK

NODE FEEDBACK

DSM2190F4

DSP SYSTEM

MEMORY

INTERNAL ADDR, DATA, CONTROL BUS LINKED TO DSP

DECODE PLD

(DPLD)

AND

ARRAY

EXTERNAL

CHIP SELECTS

JTAG-ISP

TO ALL AREAS

OF CHIP

CC C

EXTERNAL CHIP SELECTS, ESC0-2

RUNTIME CONTROL

CSIOP REGISTER FILE

POWER MANAGEMENT

CSIOP

MAIN FLASH MEMORY

8 SEGMENTS, 32 KB

256 KBytes TOTAL

fs0

fs7

2nd FLASH MEMORY

4 SEGMENTS, 8 KB

32 KBytes TOTAL

csboot0

csboot3

CSBOOT0-3

FS0-7

AD0

DSP

ADDR

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

PD0

PD1

PD2

PC7

DSP

CONTROL

CNTL0

CNTL1

CNTL2

RST\

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

DSP

DATA

PC2

AI04960B

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