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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72561J4-Auto датащи(PDF) 206 Page - STMicroelectronics |
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ST72561J4-Auto датащи(HTML) 206 Page - STMicroelectronics |
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206 / 324 page  LINSCI serial communication interface (LIN master only) ST72561-Auto 206/324 Doc ID 12370 Rev 8 Note: The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled (TE and RE = 0), the SCLK and TDO pins go into high impedance state. The LBCL, CPOL and CPHA bits have to be selected before enabling the transmitter to ensure that the clock pulses function correctly. These bits should not be changed while the transmitter is enabled. Figure 91. SCI example of synchronous and asynchronous transmission Figure 92. SCI data clock timing diagram (M = 0) Asynchronous Synchronous (e.g. modem) (e.g. shift register) RDI TDO SCLK Output port Enable Clock Data in Data in Data out SCI M = 0 (8 data bits) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1) Start LSB MSB Stop * LBCL bit controls last data clock pulse Start Idle or preceding transmission Data Stop Clock (CPOL=0, CPHA=0) 01 2 3 4 5 6 7 * * * * Idle or next transmission |
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