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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72561J4-Auto датащи(PDF) 128 Page - STMicroelectronics |
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ST72561J4-Auto датащи(HTML) 128 Page - STMicroelectronics |
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128 / 324 page  8-bit timer (TIM8) ST72561-Auto 128/324 Doc ID 12370 Rev 8 Figure 59. Timer block diagram Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFh to 00h then: ● The TOF bit of the SR register is set. ● A timer interrupt is generated if: – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: MCU-PERIPHERAL INTERFACE COUNTER ALTERNATE OUTPUT COMPARE REGISTER OUTPUT COMPARE EDGE DETECT OVERFLOW DETECT CIRCUIT 1/2 1/4 1/8 ST7 INTERNAL BUS LATCH1 OCMP1 ICAP1 fCPU TIMER INTERRUPT ICF2 ICF1 TIMD 0 0 OCF2 OCF1 TOF PWM OC1E 0 IEDG2 CC0 CC1 OC2E OPM FOLV2 ICIE OLVL1 IEDG1 OLVL2 FOLV1 OCIE TOIE ICAP2 LATCH2 OCMP2 8 8 8 8 8 8 8 (Control Register 1) CR1 (Control Register 2) CR2 (Control/Status Register) 6 8 8 8 TIMER INTERNAL BUS CIRCUIT1 EDGE DETECT CIRCUIT2 CIRCUIT 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2 CC[1:0] COUNTER pin pin pin pin REGISTER REGISTER Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table) (See note) CSR 1/8000 fOSC2 |
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