ST10F296 datasheet(200/346 Pages) STMICROELECTRONICS

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17.7

Calculation of the bit timing parameters

Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time.

The resulting bit time (1/ bit rate) must be an integer multiple of the system clock period.

The bit time may consist of four to 25 time quanta. The length of the time quantum, tq, is

defined by the baud rate prescaler, with tq = (baud rate prescaler) / fsys. Several

combinations may lead to the desired bit time, allowing iterations of the steps described

below.

The first part of the bit time to be defined is the Prop_Seg. Its length depends on the delay

times measured in the system. A maximum bus length as well as a maximum node delay

has to be defined for expandible CAN bus systems. The resulting time for Prop_Seg is

converted into time quanta (rounded to the nearest integer multiple of tq).

The Sync_Seg is 1 tq long (fixed), leaving (bit time – Prop_Seg – 1) tq for the two phase

buffer segments. If the number of the remaining tq is even, the phase buffer segments have

the same length:

Phase_Seg2

= Phase_Seg1

else:

Phase_Seg2

= Phase_Seg1 + 1.

The minimum nominal length of Phase_Seg2 has also to be considered. Phase_Seg2

should not be shorter than the CAN controller’s information processing time, which,

depending on the actual implementation, is in the range of [0...2] tq.

The length of the synchronization jump width is set to its maximum value, which is the

minimum of four times quanta and the value defined by the Phase_Seg1.

The oscillator tolerance range necessary for the resulting configuration is calculated by the

formulae given in Section 17.5: System clock tolerance range on page 196.

If more than one configuration is possible, the configuration allowing the highest oscillator or

PLL tolerance range should be chosen.

CAN nodes with different system clocks require different configurations to come to the same

bit rate. The calculation of the propagation time in the CAN network, based on the nodes

with the longest delay times, is made once for the whole network.

The CAN system’s oscillator (or PLL) tolerance range is limited by the node with the lowest

tolerance range.

The calculation may show that bus length or bit rate have to be decreased, or that the

oscillator frequency stability has to be increased to find a protocol compliant configuration of

the CAN bit timing.

The resulting configuration is written into the bit timing register:

(Phase_Seg2 - 1) &

(Phase_Seg1 + Prop_Seg - 1) &

(SynchronisationJumpWidth - 1) &

(Prescaler - 1)

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