ST10F296 datasheet(199/346 Pages) STMICROELECTRONICS

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CAN modules

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17.6

Configuration of the CAN controller

In the C-CAN and in most CAN implementations, the bit timing configuration is programmed

in two register bytes. The sum of Prop_Seg and Phase_Seg1 (as TSeg1) is combined with

Phase_Seg2 (as TSeg2) in one byte, and SJW and BRP are combined in the second byte.

In these bit timing registers (CANxBTR), the four components TSeg1, TSeg2, SJW, and

BRP have to be programmed to a numerical value that is one less than its functional value.

Therefore, instead of values in the range of [1...n], values are programmed in the range

[0...n-1]. Consequently, SJW (functional range of [1...4]) is represented by only two bits.

The length of the bit time is [TSeg1 + TSeg2 + 3] tq (programmed values) or [Sync_Seg +

Prop_Seg + Phase_Seg1 + Phase_Seg2] tq (functional values).

The data in the bit timing registers are the configuration input of the CAN protocol controller.

The baud rate prescaler (configured by BRP) defines the length of the time quantum and the

basic time unit of the bit time. The bit timing logic (configured by TSeg1, TSeg2, and SJW)

defines the number of time quanta in the bit time.

Processing of the bit time, calculation of the position of the sample point, and occasional

synchronizations are controlled by the bit timing logic (BTL) state machine, which is

evaluated once each time quantum. The rest of the CAN protocol controller, the bit stream

processor (BSP) state machine, is evaluated once each bit time, at the sample point.

The shift register serializes the messages to be sent and parallelizes received messages. Its

loading and shifting is controlled by the BSP.

The BSP translates messages into frames and vice versa. It generates and discards the

enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the cyclic

redundancy check (CRC) code, performs the error management, and decides which type of

synchronization is to be used. It is evaluated at the sample point and processes the sampled

bus input bit. The time after the sample point that is needed to calculate the next bit to be

sent (for example, data bit, CRC bit, stuff bit, error flag, or idle) is called the information

processing time (IPT).

The IPT is application specific but may not be longer than 2 tq. The C-CAN’s IPT is 0 tq. Its

length is the lower limit of the programmed length of Phase_Seg2. In case of a

synchronization, Phase_Seg2 may be shortened to a value less than IPT, which does not

affect bus timing.

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