ST10F296 datasheet(198/346 Pages) STMICROELECTRONICS

198 / 346 page

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CAN modules

ST10F296E

198/346

Considering the PLL effect, Equation 17 and Equation 18 below are modified for the two

CAN conditions to give the phase error:

Equation 17

Equation 18

Where

δPLL represents the absolute deviation introduced by the PLL jitter.

In Equation 17 and Equation 18 the value of

δPLL must be evaluated for different numbers of

clock periods. For the first clock period, the jitter corresponding to 10 bit time periods must

be considered, while for the second clock period, the jitter corresponding to 13 bit time

periods must be considered. The number of clock periods must be computed taking account

of the baud rate prescaler setting. A factor of two, which multiplies the single CAN node

phase deviation, is considered to take account of the worst case scenario where two

communicating nodes are at the opposite limits of the specified frequency tolerance.

From Equation 17 and Equation 18, the new constraints for the CAN system clock tolerance

can be translated into new quality requirements for the oscillator as shown in Equation 19

and Equation 20.

Equation 19

Equation 20

It is obvious that the PLL jitter imposes more stringent constraints on oscillator tolerance

than what can be accepted when no PLL is used. The ST10F296E PLL characteristics are

such that the oscillator requirements are acceptably impacted by the jitter for the majority of

the worst CAN bus network configurations.

Oscillator tolerance range was increased when the CAN protocol was developed from

version 1.1 to version 1.2 (version 1.0 was never implemented in silicon). The option to

synchronize on edges from dominant to recessive became obsolete and only edges from

recessive to dominant are now considered for synchronization. Protocol update to version

2.0 (A and B) has had no influence on oscillator tolerance.

It must be considered that SJW may not be larger than the smaller of the phase buffer

segments and that the propagation time segment limits the part of the bit time that may be

used for the phase buffer segments.

The combination below allows the largest possible frequency tolerance of 1.58 % (in the

absence of PLL jitter):

●

Prop_Seg = 1

●

Phase_Seg1 = Phase_Seg2 = SJW = 4

This combination with a propagation time segment of only 10 % of the bit time is not suitable

for short bit times. It can be used for bit rates of up to 125 Kbit/s (bit time = 8 µs) with a bus

length of 40 m.

∆t

2df

PLL

()

∆t

2df13

PB2

–

() δ

PLL

[]

SJW

PLL

210t

⁄

–

min t

PB1

PB2

() 2 δ

PLL

213

PB2

–

()

⁄

–

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Product(s)

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Product(s)

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