ST10F296 datasheet(197/346 Pages) STMICROELECTRONICS

197 / 346 page

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ST10F296E

CAN modules

197/346

However, considering that real systems typically operate in the presence of electrical

disturbances, errors on the CAN bus may occur. If an error is detected, an error flag is

transmitted on the bus. If the error is local, only the node which detected it transmits the

error flag on the bus; the other nodes receive the error flag and transmit their own error flags

as an echo. If the error is global, all nodes detect it within the same bit time and they

transmit their own error flags simultaneously. In this way, each node can recognize if the

error is local or global simply by detecting whether there is an echo. However, this is

possible only if each node can sample the first bit after the error flag has been transmitted.

The error flag from an error active node is composed of six dominant bits. In the worst case

situation of a bit stuffing error, an additional six dominant bits could be received before the

error flag. This means that the first bit after the error flag is the 13th bit after the last

synchronization. This bit, must be correctly sampled.

Calling tBT the CAN bit time, the maximum time, tS (with correct sampling), between two re-

synchronization edges can be expressed as shown in Equation 13.

Equation 13

Where tPB2 corresponds to the duration of Phase_Seg2 (PB = phase buffer).

Assuming that the two CAN nodes have opposite system clock generator tolerances for their

respective system clocks, Equation 14 shows the accumulated phase error,

∆tJ, at the re-

synchronization instant.

Equation 14

For correct sampling, the accumulated phase error must not lead the re-synchronization

edge outside the interval Phase_seg1 + Phase_Seg2. This condition can be expressed as

shown in Equation 15.

Equation 15

This expression can be translated to a condition for the CAN system clock tolerance, df, as

shown in Equation 16.

Equation 16

In conclusion, there are two conditions to be satisfied on the CAN system clock tolerance.

If the CAN node generates its system clock through a PLL, the maximum clock tolerance

allowed must also be a function of the PLL jitter. This results in a more severe quality

requirement for the oscillator (crystal or resonator).

The phase error introduced by the PLL jitter is a function of the number of clock periods. In

particular, the jitter increases with the clock period number up to a maximum saturation

value which consists of the long term jitter. Refer to Section 24.8.7: Phase-locked loop (PLL)

on page 315 for more details about the ST10F296E PLL jitter.

PB2

–

∆t

2df

()

PB2

–

()

PB1

2df

()

Seg2

–

() t

PB2

min t

PB1

PB2

() 213 t

PB2

–

()

⁄

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Product(s)

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