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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST10F296 датащи(PDF) 60 Page - STMicroelectronics |
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ST10F296 датащи(HTML) 60 Page - STMicroelectronics |
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60 / 346 page  Obsolete Product(s) - Obsolete Product(s) Internal Flash memory ST10F296E 60/346 Flash non-volatile access protection register 1 high (FNVAPR1H) 5.4.2 Access protection The Flash modules have one level of access protection (access to data both when reading and writing). If bit ACCP of the FNVAPR0 register is programmed at 0, the IFlash module becomes access protected: Data in the IFlash module can be read/written only if the current execution is from the IFlash module itself. Protection can be permanently disabled by programming bit PDS0 of the FNVAPR1H register to analyze rejects. Allowing PDS0 bit programming only when the ACCP bit is programmed, guarantees that only an execution from the Flash itself can disable the protections. Protection can be permanently enabled again by programming bit PEN0 of the FNVAPR1L register. Access protection can be permanantly disabled and enabled again up to 16 times. Trying to write into the access protected Flash from internal RAM is unsuccessful. Trying to read into the access protected Flash from internal RAM outputs dummy data. When the Flash module is access protected, data access through the program erase controller (PEC) of a peripheral is forbidden. To read/write data in PEC mode from/to a protected bank, the Flash module must be temporarily unprotected. Due to the ST10 architecture, the XFlash is seen as external memory. For this reason, it is impossible to access protect it from real external memory or internal RAM. Table 33 summarizes the different access protection levels. In particular, it shows what is possible (and not possible) if trying to enable all access protections when fetching from a memory (see column 1). FNVAPR1H (0x0E DFBE) NVR Delivery value: FFFFh 15 14 13 12 11 10 987 65432 10 PEN 15 PEN 14 PEN 13 PEN 12 PEN 11 PEN 10 PEN 9 PEN 8 PEN 7 PEN 6 PEN 5 PEN 4 PEN 3 PEN 2 PEN 1 PEN 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 32. FNVAPR1H register description Bit Bit name Function 15-0 PEN[15:0] Protections enable 15-0 If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, bit ACCP action is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has already been programmed at 0. Obsolete Product(s) - Obsolete Product(s) |
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