ST10F296 datasheet(196/346 Pages) STMICROELECTRONICS

196 / 346 page

Obsolete

Product(s)

- Obsolete

Product(s)

CAN modules

ST10F296E

196/346

17.5

System clock tolerance range

The CAN system clock for the different nodes in the network is typically derived from a

different clock generator source. The actual CAN system clock frequency for each node

(and consequently the actual bit time), is affected by a tolerance. The CAN system clock for

the ST10F296E is derived (prescaled) from the CPU clock, typically generated by the on-

chip PLL multiplying the frequency of the main oscillator.

For communication to be effective, all CAN nodes in the network should sample the correct

value for each transmitted bit. In addition, those nodes with the largest propagation delay

(typically at opposite ends of the network), and working with system clocks that are at

opposite limits of the frequency tolerance, must be able to correctly receive and decode

every message transmitted on the network.

Considering the effect of the system clock discrepancy between two CAN nodes, and

assuming no bus errors are detected (for example, due to electrical disturbances), bit

stuffing guarantees that, in the worst case condition for the accumulation of phase error

(during normal communication), the maximum time between two re-synchronization edges

is 10 bit periods (five dominant bits followed by five recessive bits are always followed by a

dominant bit).

Calling the CAN bit time, tBT, the maximum time, tJ, between two re-synchronization edges

can be expressed as follows:

Equation 8

Then, assuming that the two CAN nodes have opposite system clock generator tolerances

for their respective system clocks, the accumulated phase error,

∆tJ, at the re-

synchronization instant becomes:

Equation 9

Where df is the system clock relative tolerance which can be calculated from Equation 10:

Equation 10

f = actual frequency and fN = nominal frequency.

The error in Equation 10 must be compensated. It must be less than the programmed

resynchronization jump width (SJW). Calling tSJW the duration of the resynchronization

segment (programmable from 1 to 4 time quanta), Equation 11 can be written.

Equation 11

Equation 11 can be seen as a condition for the CAN system clock tolerance, df, as shown in

Equation 12.

Equation 12

∆t

2df

() 10 t

–

⁄

2df

() 10 t

SJW

210

⁄

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296 датащи(PDF) 196 Page - STMicroelectronics

ST10F296 датащи(HTML) 196 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL