ST10F296 datasheet(192/346 Pages) STMICROELECTRONICS

192 / 346 page

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CAN modules

ST10F296E

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CAN modules

The two integrated CAN modules (CAN1 and CAN2) are identical and handle the

autonomous transmission and reception of CAN frames according to the CAN specification

V2.0 part B (active). It is based on the C-CAN specification.

Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers

and extended frames with 29-bit identifiers.

Because of duplication of the CAN controllers, the following adjustments must be

considered:

●

Use the same internal register addresses for both CAN controllers, but, with base

addresses differing in address bit A8. Also, use a separate chip select for each CAN

module. Refer to Section 4: Memory organization on page 33.

●

The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and

the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin.

●

The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and

the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin.

●

The interrupt request lines of the CAN1 and CAN2 modules are connected to the XBus

interrupt lines with other XPeripherals sharing the four vectors.

●

The CAN modules must be selected with the CANxEN bit of the XPERCON register

before the XPEN bit of the SYSCON register is set.

●

The reset default configuration is: CAN1 enabled, CAN2 disabled.

17.1

CAN module memory mapping

17.1.1

CAN1

Address range 00’EF00h - 00’EFFFh is reserved for CAN1 module access. CAN1 is

enabled by setting the XPEN bit of the SYSCON register and by setting bit 0 of the

XPERCON register. Accesses to the CAN module use demultiplexed addresses and a 16-

bit data bus (byte accesses are possible). Two wait states give an access time of 62.5 ns at

64 MHz CPU clock. No tri-state wait states are used.

17.1.2

CAN2

Address range 00’EE00h - 00’EEFFh is reserved for CAN2 module access. CAN2 is

enabled by setting the XPEN bit of the SYSCON register and by setting bit 1 of the

XPERCON register. Accesses to the CAN module use demultiplexed addresses and a 16-

bit data bus (byte accesses are possible). Two wait states give an access time of 62.5 ns at

64 MHz CPU clock. No tri-state wait states are used.

Note:

If one or both CAN modules is used, Port 4 cannot be programmed to output all eight

segment address lines. Thus, only four segment address lines can be used, reducing the

external memory space to 5 Mbytes (1 Mbyte per CS line).

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