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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ENICSF2811PBKA датащи(PDF) 110 Page - Texas Instruments |
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ENICSF2811PBKA датащи(HTML) 110 Page - Texas Instruments |
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110 / 172 page  t d(WAKE-STBY) t d(IDLE-XCOH) 32 SYSCLKOUT Cycles Wake-up Signal X1/XCLKIN XCLKOUT Flushing Pipeline A B C D E F Device Status STANDBY Normal Execution STANDBY t w(WAKE-INT) TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174T – APRIL 2001 – REVISED MAY 2012 www.ti.com A. IDLE instruction is executed to put the device into STANDBY mode. B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off: • 16 cycles, when DIVSEL = 00 or 01 • 32 cycles, when DIVSEL = 10 • 64 cycles, when DIVSEL = 11 This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its access time is longer than this number, then it will fail. It is recommended that STANDBY mode be entered from SARAM without an XINTF access in progress. C. Clocks to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. D. The external wake-up signal is driven active. E. After a latency period, the STANDBY mode is exited. F. Normal execution resumes. The device will respond to the interrupt (if enabled). Figure 6-16. STANDBY Entry and Exit Timing 110 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 |
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