ENICSF2811PBKA datasheet(151/172 Pages) TI1

151 / 172 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174T – APRIL 2001 – REVISED MAY 2012

Table 6-51. McBSP Switching Characteristics(1)(2)

NO.

PARAMETER

MIN

MAX

UNIT

tc(CKRX)

Cycle time, CLKR/X

CLKR/X int

tw(CKRXH)

Pulse duration, CLKR/X high

CLKR/X int

D – 5(3)

D + 5(3)

tw(CKRXL)

Pulse duration, CLKR/X low

CLKR/X int

C – 5(3)

C + 5(3)

CLKR int

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR ext

CLKX int

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX ext

CLKX int

Disable time, CLKX high to DX high impedance following last

tdis(CKXH-DXHZ)

data bit

CLKX ext

CLKX int

Delay time, CLKX high to DX valid.

This applies to all bits except the first bit transmitted.

CLKX ext

CLKX int

td(CKXH-DXV)

DXENA = 0

Delay time, CLKX high to DX valid.

CLKX ext

Only applies to first bit transmitted when in Data

CLKX int

P + 8

Delay 1 or 2 (XDATDLY = 01b or 10b) modes.

DXENA = 1

CLKX ext

P + 14

CLKX int

DXENA = 0

Enable time, CLKX high to DX driven.

CLKX ext

ten(CKXH-DX)

Only applies to first bit transmitted when in Data

CLKX int

Delay 1 or 2 (XDATDLY = 01b or 10b) modes.

DXENA = 1

CLKX ext

P + 6

FSX int

DXENA = 0

Delay time, FSX high to DX valid.

FSX ext

td(FXH-DXV)

Only applies to first bit transmitted when in Data

FSX int

P + 8

Delay 0 (XDATDLY = 00b) mode.

DXENA = 1

FSX ext

P + 14

FSX int

DXENA = 0

Enable time, FSX high to DX driven.

FSX ext

M10

ten(FXH-DX)

Only applies to first bit transmitted when in Data

FSX int

Delay 0 (XDATDLY = 00b) mode.

DXENA = 1

FSX ext

P + 6

(1)

Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that

signal are also inverted.

(2)

2P = 1/CLKG in ns.

(3)

C = CLKRX low pulse width = P

D = CLKRX high pulse width = P

Electrical Specifications

151

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