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STV2050A - MASTER I²C BUS INTERFACE

6 MASTER I²C BUS INTERFACE

A master I²C bus implemented in the STV2050A is used to transfer data between the IC em-

bedded RAM and the external 2K x 8-bit EEPROMs (for example, the 24164 manufactured by

ST). The protocol supports up to 7 EEPROM addresses which can be selected using the 3

EEPROMadd[2:0] bits in the E9 register.

Master activities are initiated either by an external reset of the STV2050A, or by commands

from an external MCU via the Slave I²C bus. The following features are implemented in the

Master I²C Bus interface:

– Reset the I²C bus to the EEPROM

– Read a specified data range from EEPROM to RAM

– Write a specified data range from RAM to EEPROM

– Check if an EEPROM register is available

– Power-on sequence

– Security features

– Generate status information

The organization of data in the embedded RAM is completely different from that in the

EEPROM register. Therefore, address transformations are required in both directions. This is

carried out by the STV2050A in a way that is fully transparent for the user.

The external MCU initiates a master access to the EEPROM by writing a command to the E9

address. This command contains information about the type of access and specifies one of

seven EEPROMs (refer to Section 6.6 "DATA TRANSFER BETWEEN RAM AND EEPROM"

on page 30).

The embedded RAM contains convergence correction data and one adjustment data set

(ADS) to control the various modes of the STV2050A. Three ADSs can be stored in the

EEPROM. One of these three sets is selected by the two ADS[1:0] bits in the E9 command to

be mapped to the register RAM area inside the IC.

Any command sent from the MCU to the E9 address while the master is active will be lost.

Also, the EEPROM address which is included in this command will not be accepted.

Before addressing the E9 register, the MCU should check if the master is active. To do this,

the RWM[2:0] bits in the E9 register must be set to “001” (bin). The corresponding status is

given on the STX[2] bit.

If any error are detected during the transmission of data on the EEPROM I²C bus, the trans-

mission is stopped and the corresponding STX[3] bit of the status section of the E9 register is

set.

Read or Write modes can be selected by setting bit RWM[2] in the E9 register.

RWM[2]

0 = Read mode

1 = Write mode

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