STV2050A datasheet(25/83 Pages) STMICROELECTRONICS

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STV2050A - TIMEBASES

Autocalibration can take place either during the full line, or during the line retrace only. This is

controlled by the ACW bit in the D8 register.

If the “During Line Retrace Only” autocalibration is selected, the number of DAC cells cali-

brated during each line retrace is defined by the AFS[1:0] value in the D8 register.

Two autocalibration modes can be selected by the AMS[0] bit in the D5 register.

The time interval for auto-calibration is normally centred to the retrace. But it is possible to ad-

just the start point by programming the ASP[2:0] bits in the D8 register. One step corresponds

to one system clock cycle.

5.4 VERTICAL TIME BASE

5.4.1 Vertical Synchronization Signal

The vertical timing is based on the vertical deflection signal. A debounce filter is implemented

to prevent interference on the SYNV signal caused by crosstalk, mainly from horizontal deflec-

tion. This filter accepts a rising edge of the SYNV signal only when SYNV is 'LOW' for a time

≥ 8 TV lines (determined by 8 pulses at the SYNH input).

Figure 12. Vertical Synchronization Signal

ACL[1:0]

00: No calibration

01: Division by 16

10: Division by 32

11: Division by 48

ACW

0: During line retrace only

1: During the full line

AFS[1:0]

00: 1 cell / line

01: 2 cells / line

10: 3 cells / line

11: 4 cells / line

AMS[0]

0: The autocalibration process is not synchronized to vertical timing

1: The autocalibration is synchronized to vertical IC timing. The counter

which selects the DAC cells that are to be calibrated is reset on each

frame retrace.

> 8H

V - deflection

SYNV

VSYNC

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